Freescale Semiconductor StarCore SC140 - Manual (Page 159)

EOnCE Controller Registers
SC140 DSP Core Reference Manual 4-49
4.7.8 PC of the Exception Execution Set (PC_EXCP)
PC_EXCP enables the user to determine exactly which execution set caused an imprecise internal Illegal
or DALU overflow exception. It is a read-only register that is accessed through the JTAG port or by core
software.
In the case of an illegal instruction, illegal execution set or DALU overflow, the PC of the execution set is
saved in the PC_EXCP register. In this way, users can determine the address of the execution set that
caused the internal exception. It is best done in the illegal exception service routine, which is serviced right
after the exception event has occurred. For a list of internal exceptions, see
Section 5.8, “Exception
Processing,” on page 5-46.
Multiple exception events may occur between the first event and its exception service routine. For multiple
exception types (illegal or DALU overflow), the PC_EXCP register will capture the VLES address of the
first occurrence of the last exception type, regardless of whether the exception type is serviced or not. For
multiple events of the same type (including the different reasons of the illegal exception), only the first
event will be sampled in PC_EXCP.
4.7.9 PC of the Next Execution Set (PC_NEXT)
PC_NEXT is a 32-bit register that stores the address of the execution set to be executed next. Although the
PC_NEXT register can also be read while the device is running and not in debug state, the register contents
are not defined. This register is not affected by the operations performed during debug state. When single
stepping, the value of PC_NEXT is valid after every step. PC_NEXT will sample data only if the EOnCE
is enabled (see
Section 4.4, “EOnCE Enabling and Power Considerations.” ) If the EOnCE enters debug
state without being enabled first, the value of PC_NEXT is undefined.
PC_NEXT is read-only and read through JTAG.
4.7.10 PC of Last Execution Set (PC_LAST)
PC_LAST contains the PC of the last executed execution set. It is used in debug state to define which PC
triggered a PC breakpoint. If the PC_LAST register is read while the device is running and not in debug
state, the register contents are not defined. PC_LAST will sample data only if the EOnCE is enabled (see
Section 4.4, “EOnCE Enabling and Power Considerations.” ) If the EOnCE enters debug state without
being enabled first, the value of PC_LAST is undefined. In case of a killed PC (when PCKILL in ESR is
asserted), the value of PC_LAST is not updated to that of the killed PC, and still reflects the last execution
set.
PC_LAST is read-only and read through JTAG.
4.7.11 PC Breakpoint Detection Register (PC_DETECT)
PC_DETECT captures the PC value of the first execution set that caused an entry into debug state based on
a data memory event in EDCA or EDCD. For data breakpoint detection, only the first event will be
sampled into PC_DETECT because the core has already executed a few more execution sets by the time it
enters debug state.
PC_DETECT captures the correct PC of the VLES that triggered the entry into debug state if all the
following conditions are met:
• An event was detected on XABA/B and/or XDBA/B by an enabled EDCA/D channel.