Freescale Semiconductor StarCore SC140 - Manual (Page 128)

4-18 SC140 DSP Core Reference Manual
EOnCE Module Internal Architecture
The functionality of the EOnCE controller registers is described in Section 4.7, “EOnCE Controller
Registers.”
4.5.2 Event Counter
The 64-bit event counter is used to count one of the following possible events:
• System clock
• Instruction execution
• Event detection by an event detection channel
• Tracing into the trace buffer
• Execution of the DEBUGEV instruction
• Off-core events from the EC input signals
When the core is in debug state, the event counter does not count core clocks.
The event counter programming model includes three registers:
• Event counter register (ECNT_CTRL)
• Downcount event counter value register (ECNT_VAL)
• Extension counter value register (ECNT_EXT)
PC_NEXT PC of the next execution set
PC_LAST PC of the last execution set
PC_DETECT PC breakpoint address register
Table 4-6. EOnCE Controller Register Set
Register Name Description