Freescale Semiconductor StarCore SC140 - Manual (Page 493)

ILLEGAL
SC140 DSP Core Reference Manual A-179
Status and Conditions that Affect Instruction
None.
Status and Conditions Changed by Instruction
Example
illegal
Instruction Formats and Opcodes
Register Address Bit Name Description
SR[18] EXP Sets EXP to switch active stack pointer to exception stack pointer.
SR[23:21] I[2:0] Set interrupt priority level to 111.
EMR [0] ILIN Sets illegal instruction bit.
SR[0] C Cleared
SR[1] T Cleared
SR[5:4] S[1:0] Cleared
SR[31] SLF Cleared
SR[30:27] LF[3:0] Clear loop flags.
Register/Memory Address Before After
SR $18E0 0003 $00E4 0000
EMR $0000 0000 $0000 0001
Instruction Words Cycles
1
Note 1: Cycle count is dependant on the machine state. Typically, five cycles is the service time for an illegal
request.
Type Opcode
15 8 7 0
ILLEGAL 1 4 5 1 0 0 1 1 1 1 0 0 1 1 1 1 1 0 0