Freescale Semiconductor StarCore SC140 - Manual (Page 63)

Address Generation Unit
SC140 DSP Core Reference Manual 2-31
2.3 Address Generation Unit
The AGU is one of the execution units in the SC140 core. The AGU performs effective address
calculations using the integer arithmetic necessary to address data operands in memory. It also contains the
registers used to generate the addresses. The AGU implements four types of arithmetic: linear, modulo,
multiple wrap-around modulo, and reverse-carry. It operates in parallel with other chip resources to
minimize address generation overhead. The AGU also generates change-of-flow program addresses as
well as updates the stack pointer (SP), whenever needed.
2.3.1 AGU Architecture
The major components of the AGU are listed below:
• Eight low bank address registers (R0–R7)
• Eight high bank address registers (R8–R15), or alternatively, eight base address registers (B0–B7)
• Two stack pointers (NSP, ESP), only one of which is active at a time (SP)
• Four offset registers (N0–N3)
• Four modifier registers (M0–M3)
• A modifier control register (MCTL)
• Two address arithmetic units (AAU)
• One bit mask unit (BMU)
In this section, the registers are referred to as:
• Rn for any of the R0–R15 address registers
• Bn for any of the B0–B7 base address registers
• Ni for any of the N0–N3 offset registers
• Mj for any of the M0–M3 modifier registers
All the Rn, Bn, SP, Ni, and Mj registers are referred to as AGU registers. All of the AGU registers are
32-bits.
Figure 2-12 shows a block diagram of the AGU.