Lsrr, Multiple-bit bitwise shift right (dalu), Operation assembler syntax – Freescale Semiconductor StarCore SC140 User Manual
Page 542
A-228
SC140 DSP Core Reference Manual
LSRR
LSRR
Multiple-Bit Bitwise Shift Right (DALU)
LSRR
|Description
Status and Conditions that Affect Instruction
None.
Operation
Assembler Syntax
If Da[6:0] > 0, then Dn>>>Da
→ Dn
else Dn
<< ⏐Da⏐→ Dn
LSRR Da,Dn {–40
≤ Da[6:0] ≤ 40}
Dn
>>> #u5 → Dn
LSRR #u5,Dn {0
≤ u5 < 32}
LSRR Da,Dn
Logically shifts the contents of a 40-bit data register (Dn) left or right N bits. N is a signed 6-bit integer
contained in Da bits [6:0].
If N is positive, Dn is shifted right. Bit (N – 1) is stored in the C bit. Bits [39:N] are copied to bits [(39 –
N):0]. Bits [39:(40 – N)] are cleared.
If N is negative, Dn is shifted left. Bit (40 – |N|) is stored in the C bit. Bits [(39 – |N|):0] are copied to bits
[39:|N|]. Bits [(|N| – 1):0] are cleared.
LSRR #u5,Dn
Shifts the contents of a 40-bit data register (Dn) right the number of bits designated in #u5. #u5 is an
unsigned 5-bit integer immediate. Bit (N – 1) is stored in the C bit. Bits[ 39:N] are copied to bits [(39 –
N):0]. Bits [39:(40 – N)] are cleared.
0
0
15
16
31
32
39
C
0
15
16
31
32
39
C
Da[6:0]
> 0
Da[6:0]
≤
0
0
0
15
16
31
32
39
C
0