Freescale Semiconductor StarCore SC140 - Manual (Page 40)

2-8 SC140 DSP Core Reference Manual
DALU
2.2.1.1 Data Registers (D0–D15)
In this section, the D0–D15 data registers are referred to as Dn. They can be used as:
• Source operands
• Destination operands
• Accumulators
The registers can serve as input buffer registers between XDBA or XDBB and the ALUs. The registers are
used as DALU source operands, allowing new operands to be loaded for the next instruction while the
register contents are used by the current arithmetic instruction.
Each data register Dn has a limit tag bit (Ln) which is used to signify whether the extension portion of the
register is in use. The limit tag bit Ln is coupled to the extension portion Dn.e, which forms a 9-bit operand
for the purpose of storing these bits to memory. See
Section 2.2.1.6, “Limiting,” for further details.
The data registers can be accessed over XDBA and XDBB with three data widths:
• A long-word access, writing or reading 32-bit operands
• A word access, writing or reading 16-bit operands
• A byte access, writing or reading 8-bit operands
For move instructions of fractional data, the transfer of a Dn register to memory over XDBA and XDBB is
protected against overflow by substituting a limiting constant for the data that is being transferred. The
content of Dn is not affected should limiting occur. Only the value transferred over XDBA or XDBB is
limited. This process is commonly referred to as transfer saturation and should not be confused with the
arithmetic saturation mode as described in
Section 2.2.2.7, “Arithmetic Saturation Mode.”
Limiting is performed after the contents of the register have been shifted according to the scaling mode.
Shifting and limiting are performed only for MOVES instructions when a fractional operand is specified as
the source for a data move over XDBA or XDBB. When an integer operand is specified as the source for a
data move, shifting and limiting are not performed.
Automatic sign extension (or zero extension of the data values into the 40-bit registers) is provided when
an operand is transferred from memory to a data register. Sign extension can occur when loading the Dn
register from memory. If a fractional word operand is to be written to a data register, the high portion (HP)
of the register is written with the word operand. The low portion (LP) is zero-filled. The EXT portion is
sign-extended from the HP, and the limit tag bit (Ln) is cleared.
When an integer word operand is to be written to a data register, the LP portion of the register is written
with the word operand. The HP and EXT portions are either zero-extended or sign-extended from the LP.
Long-word operands are written into the HP:LP portions of the register. The EXT portion is zero-extended
or sign-extended, and the limit tag bit (Ln) is cleared.
When a byte operand is to be written to a data register, the register’s first 8-bit portion of the LP
(Dn.1[7:0]) is written with the byte operand. The following eight bits of the LP (Dn.1[15:8]), the high
portion, and the EXT are either zero-extended or sign-extended from the LP lower byte. The limit tag bit
(Ln) is cleared.