Freescale Semiconductor StarCore SC140 - Manual (Page 160)

4-50 SC140 DSP Core Reference Manual
Event Counter Registers
• This event was programmed in ESEL_DM.
• The debug reason bits (DREDCA0-5, DREDCD) in ESR indicate that the data detection event was
part of the reason to enter debug state. ESR should be checked because ESEL_DM may be
programmed to enter debug state for other reasons that do not cause sampling into PC_DETECT.
This ESR check should match the way the data memory events were programmed to combine to a
debug entry condition in ESEL_CTRL. For example, several conditions could be ANDed or ORed,
requiring a different ESR check in each case.
Once sampled, PC_DETECT will not be re-sampled again until the core enters and then exits debug state.
PC_DETECT is read-only and read through JTAG or by core software. PC_DETECT should be read only
in debug state. If PC_DETECT is read when the core is not in debug state, its value is undefined.
4.8 Event Counter Registers
The event counter (ECNT) contains three registers:
• Event Counter Register (ECNT_CTRL)
• Event Counter Value Register (ECNT_VAL)
• Extension Counter Value Register (ECNT_EXT)
These three registers are described in the following sections.
4.8.1 Event Counter Control Register (ECNT_CTRL)
The ECNT_CTRL register selects the event to be counted by the event counter. It also determines the
enabled source of the event counter.
Two modes of event counter operation are determined by the ECNT_CTRL register:
1. In the regular mode of operation, the extension counter is disabled. Thus, when the event
counter reaches zero, the count event is generated and the counter stops its operation. The
maximum value that can be counted before generating the count event is $8000 0000. This
can be achieved by writing $0000 0000 to the ECNT_VAL register. The event counter can be
used as a watchdog timer provided that the counter is programmed to count the DSP cycles
(internal clock), and that the debug exception in the ES event is set to generate an EOnCE
event upon count event (when the counter comes to zero).
2. In the extended mode of operation, when the event counter reaches zero, it does not generate
the count event and wraps around to $7FFF FFFF. The event counter continues to count
down, and the number of transitions from 1 to 0 is counted by the extension counter. This
creates a virtual 62-bit counter. When the extension counter (ECNT_VAL) reaches $7FFF
FFFF, the next count wraps around to $0000 0000. Overflow of the extension counter
register does not generate a count event.
For information on events 0–5, see Section 4.9.1, “Address Event Detection Channel (EDCA).” For
information on event D, see Section 4.9.2, “Data Event Detection Channel (EDCD).” Like EDU, the event
counter can be enabled explicitly by writing 1111 to the ECNTEN bits of the control register. It can also be
enabled by specifying an event. The profiler can exploit this capability for cycle count operations to