Freescale Semiconductor StarCore SC140 - Manual (Page 268)

7-18 SC140 DSP Core Reference Manual
Static Programming Rules
If the VLES having a JT/JF or TRAP instruction is at the end of a program section, the following VLES
must be a NOP. It cannot be data tables or uninitialized memory.
Rule A.4
An AGU arithmetic instruction that writes a Rn or Nn register, or a MOVE-like instruction that writes a Rn
or Nn register as an address operand, cannot be grouped in a VLES with a MOVE-like instruction that
reads the same register as a data operand. For mutually exclusive IFc subgroups in a VLES, this rule
applies independently to each subgroup.
Example 7-27. Rn or Nn Write to MOVE-like Use
adda #$5,r0 move.w r0,($100) ;not allowed
move.w (r0)+,d0 bmtsts #$1234,r0.l ;not allowed
tfra r1,r0 push r0 ;not allowed
tfra r1,n0 move.l n0,d0 ;not allowed
tfra osp,r0 move.l r0,d0 ;not allowed
move.w r0,(r0)+ ;not allowed
move.w d0,(r8)+ move.l r8,d1 ;not allowed
move.w d0,(r8)+ move.l b0,d1 ;not allowed - b0 alias
vsl.2w d1:d3,(r0)+n0 move.l r0,d0 ;not allowed
move.w (r2),r0 move.w r0,(r1) ;allowed
move.w r0,(r0) ;allowed - no Rn write
adda #>28,r6,r0 move.l (r0),r2 ;allowed
adda #>28,r6,r0 move.l r2,(r0) ;allowed
adda #>5,n0 move.l d0,(r0)+n0 ;allowed
adda #>5,n0 move.l (r0)+n0,d0 ;allowed
adda #>5,n0 move.l d0,(r0+n0) ;allowed
adda #>5,n0 move.l (r0+n0),d0 ;allowed
ift adda #<1,r0 iff move.l r0,d0 ;allowed
iff adda #<1,r0 ifa movet r0,r7 ;allowed
A DOENn or DOENSHn, CONT, or CONTD instruction that writes an LCn register cannot be grouped in
a VLES with a MOVE-like instruction that reads the same register. For mutually exclusive IFc subgroups
in a VLES, this rule applies independently to each subgroup.
Example 7-28. LCn Write to MOVE-like Use
doen0 r0 move.l lc0,d0 ;not allowed
doensh0 #5 push lc0 ;not allowed
cont move.l lc1,d3 ;not allowed
contd push lc2 ;not allowed