Freescale Semiconductor StarCore SC140 - Manual (Page 727)

TRAP
SC140 DSP Core Reference Manual A-413
Status and Conditions Changed by Instruction
Example 1
trap
Instruction Formats and Opcodes
Register Address Bit Name Description
SR[18] EXP Set
SR[0] C Cleared
SR[1] T Cleared
SR[5:4] S[1:0] Cleared
SR[31] SLF Cleared
SR[30:27] LF[3:0] Cleared
SR[23:21] I[2:0] Set interrupt priority level to 111.
Register/Memory Address Before After
ESP $0000 8030 $0000 8038
VBA $8000 0000
($8034) $00E0 0000
($8030) $0000 0014
PC $0000 0012 $8000 0000
SR $00E0 0000 $00E4 0000
Instruction Words Cycles Type Opcode
15 8 7 0
TRAP 1 5 4 1 0 0 1 1 1 1 0 0 1 1 1 1 1 1 0