Appendixb starcore registry, B.1 using the starcore registry, Appendix b – Freescale Semiconductor StarCore SC140 User Manual
Page 747: Appendix b, “starcore registry, Shows, Appendix b starcore registry
SC140 DSP Core Reference Manual
Appendix B
StarCore Registry
The StarCore registry (SCR) is a system that identifies the core version.
B.1 Using the StarCore Registry
The SCR is to be used for debugging software and run-time software. A StarCore Identification number,
SCID, is encoded in bits 23-17 of the EOnCE Status Register (ESR). This 32-bit, memory-mapped,
read-only register is located at offset 00 from the EOnCE register base address defined by each
System-on-a-Chip (SoC) derivative. The SCID can be read through the JTAG standard test interface or
run-time software using the MOVE instruction. The SCID binary value can be placed in a data register by
reading ESR, shifting right by 17 bits, and ANDing the result with a $0000 007F mask. Reading ESR using
SC100 instructions does not activate the EOnCE block, thus saving power in actual operation.
An example code sequence is:
move.w ($00800002),d4
;reads from memory location of high portion ESR, assuming
that the EOnCE base address is $0080 0000. Bits 31-16 of
the ESR go to bits 15-0 of D4.
lsr d4
;shifts right 1 bit
and #0,d4.h
;clears high portion
and #$007f,d4.l
;clears bits 15-7, leaves the SCID in data register d4
The SCID has three fields:
•
REVNO (bits 23-21) instruction set version
•
RESERVED (bit 20) - 0 in Freescale implementations
•
CORETP (bits 19-17) core architecture version
The REVNO field generally identifies the basic instruction set revision of the SC100 core. It identifies the
availability of new instructions and corrections to existing instructions. Binary-encoded programs will
generally run without modification on later versions of the instruction set. Changes in REVNO imply a
software tools switch, different software simulator and different host debugger.
The CORETP field identifies the architecture member within the SC100 family. It identifies the
availability of new execution units and VLES grouping capabilities. Note that execution units and VLES
can scale up or down without altering the basic instruction set. Changes in CORETP imply a software tools
switch, different software simulator and different host debugger.
The following table lists current assignments of REVNO and CORETP. The Tools column lists the first
version of StarCore software development tools to support the listed Instruction Set Version.