Freescale Semiconductor StarCore SC140 - Manual (Page 178)

4-68 SC140 DSP Core Reference Manual
Trace Unit Registers
TLOOP
Bit 5 Trace Loops Mode — Enables tracing
the addresses of hardware loops. When
the bit is set, every change of flow
resulting from a loop puts the last
address of loop (LA) into the trace
buffer. In the case of a long loop, the
start address of loop (SA) is put into the
trace buffer after LA. If the loop has a
number of iterations N, the LA and SA of
the loop are written to the trace buffer
(N-1) times. The last iteration of the loop
is executed in normal flow. If LC = 0 or
LC = 1, LA and SA are not written to the
trace buffer. 0 = Loop tracing is disabled.
1 = Loop tracing is enabled.
For long loops, tracing includes LA, SA and optional
counter values.
For short loops, tracing includes only the PC of the loop LA
TEN
Bit 4 Trace Buffer Enable Mode — Enables
tracing. The TEN bit can be set or
cleared directly. It can also be set when
TB is enabled by the ES_ETB. It is
cleared when disabled by the ES_DTB. 0 = Tracing is disabled.
1 = Trace is enabled.
TMARK
Bit 3 Trace Mark Instruction Mode —
Enables the trace of MARK instruction
execution. 0 = MARK instruction is not traced.
1 = PC of MARK instruction is traced.
TEXEC
Bit 2 Trace Issue of Execution Sets Enable
Mode — Enables tracing the addresses
of every issued execution set. 0 = Execution set tracing is disabled.
1 = Execution set tracing is enabled. All other mode bits
should be cleared.
Tracing includes the PC of every issued execution set.
TINT
Bit 1 Trace Interrupts Enable Mode — Used
to enable tracing the addresses of
interrupt vectors. When the bit is set,
each service of an interrupt puts the
address of the last executed or aborted
execution set (before the interrupt) into
the trace buffer as well as the address of
the interrupt vector. 0 = Interrupt tracing is disabled.
1 = Interrupt tracing is enabled.
Tracing includes source PC of interrupt point, the PC
of the interrupt vector, and optional counter values
TCHOF
Bit 0 Trace Addresses of Change-of-Flow
(COF) Instructions Enable Mode —
Used to enable the tracing of addresses
for execution sets containing
change-of-flow instructions. When the
bit is set, every execution of an
execution set containing change-of-flow
instructions (even if the change-of-flow
instruction is executed together with
other instructions in the execution set)
puts into the trace buffer the address of
that execution set (the address of the
first instruction in the execution set) and
the target address of the change-of-flow
instruction. 0 = Tracing of COF instructions is disabled .
1 = Tracing of COF instructions is enabled.
Tracing includes source PC, destination PC and
optional counter value.
Table 4-23. TB_CTRL Description (Continued)
Name Description Settings