Freescale Semiconductor StarCore SC140 - Manual (Page 267)

Static Programming Rules
SC140 DSP Core Reference Manual 7-17
Rule A.2
At least one cycle is required between a MOVE-like instruction writing to an address register (Rn or Nn) as
a data operand and when the same register is used in the following manner with the following instructions:
• An address operand of a MOVE-like instruction.
• A source operand of an AGU arithmetic instruction.
• An operand holding a target of a COF instruction
1
.
This rule does not apply when a MOVE-like instruction writes Bn or Mn and used for modulo calculation
on Rn, by either MOVE or an AGU arithmetic instruction is the instruction immediately following the
MOVE-like instruction (even in the case that Bn is referred to as Rn+8)
2
. The rule does apply to writing to
Rn (for n = 8÷15), using Bn-8 representation
3
.
Example 7-26. Rn, Nn, Mn Write to AGU Use
move.l d0,r0
jmp r0
;not allowed
move.l d0,r0
move.w (r0),d1
;not allowed
move.l d0,b0
move.w (r8),d1
;not allowed (b0 is alias of r8)
move.l d0,b0
move.w (r0)+,d1
;allowed - (but may contradict Rule A.2a due to r0 post inc)
move.l d0,r0
bmclr.w #4,(r0)
;not allowed
move.l d0,b0
move.w (r0),d1
;allowed - no Rn write
move.l d0,b0
adda r9,d0
;not allowed
move.l d0,b3
adda r11,d2
;not allowed - (b3 is alias of r11)
move.l d0,m0
move.w (r0),d1
;allowed - no Rn write
move.l d0,m1
move.l d1,(r0)+
;allowed (but may contradict Rule A.2a due to r0 post inc)
move.l d0,n0
move.b (r0+n0),d1
;not allowed
Rule A.3
A VLES having a JT/JF or BT/BF or TRAP instruction must be followed by another VLES. The last VLES
in a program section cannot contain a JT/JF or TRAP instruction.
1. i.e. JMP Rn, JMPD Rn, JSR Rn, JSRD Rn, JT Rn, JTD Rn, JF Rn and JFD Rn, DOENn Rn or DOENSHn Rn
2. Writing to Bn and Mn is covered by dynamic rule A.2a.
3. B and R aliasing is applicable for other rule exceptions as well. See
Chapter 7.4.3.2, “B Register Aliasing,” for more details.