Freescale Semiconductor StarCore SC140 - Manual (Page 36)

2-4 SC140 DSP Core Reference Manual
Architecture Overview
The AGU in the SC140 core has two address arithmetic units (AAU) to allow two address generation
operations at every clock cycle. The AAU has access to:
• Sixteen 32-bit address registers (R0–R15), of which R8–R15 can also be used as base address
registers for modulo addressing.
• Four 32-bit offset registers (N0–N3).
• Four 32-bit modulo registers (M0–M3).
The two AAUs are identical. Each contains:
• A 32-bit full adder, used for offset calculations.
• A second 32-bit full adder, used for modulo calculations.
Each AAU can update one address register in the address register file in one instruction cycle.
The AGU also contains a 32-bit modulo control register (MCTL). This control register is used to specify
the addressing mode of the R registers: linear, reverse-carry, modulo, or multiple wrap-around modulo.
When modulo addressing mode is selected, the MCTL register is used to specify which of the four modulo
registers is assigned to a specific R register.
Explicit instructions in the SC140 instruction set are used to execute arithmetic operations on the address
pointers. This capability can also be used for general data arithmetic. In addition, the AGU generates
change-of-flow program addresses and updates the stack pointers as needed.
2.1.2.1 Stack Pointer Registers
Two special registers with special addressing modes are used for software stacks. These are the Normal
mode stack pointer (NSP) and the Exception mode stack pointer (ESP). Both the ESP and the NSP are
32-bit read/write address registers with pre-decrement and post-increment updates. Both are offset with
immediate values to allow random access to a software stack.
The ESP is used by stack instructions when the SC140 is in the Exception mode of operation, which is
entered when exceptions occur. The NSP is used in Normal mode when there are no exceptions. The
existence of two stack pointers enables separate allocation of stack space by the operating system and each
application task, which optimizes memory use in multi-tasking systems.
2.1.2.2 Bit Mask Unit (BMU)
The BMU provides an easy way of setting, clearing, inverting, or testing a selected, but not necessarily
adjacent, group of bits in a register or memory location.
The BMU supports a set of bit mask instructions that operate on:
• All AGU pointers (R0–R15)
• All DALU registers (D0–D15)
• All control registers (EMR, VBA, SR, MCTL)
• Memory locations
Only a single bit mask instruction is allowed in any single execution set since only one execution unit
exists for these instructions.
A subgroup of the bit mask instructions (BMTSET) provides hardware support of semaphoring, providing
one instruction for read-modify-write.