Freescale Semiconductor StarCore SC140 - Manual (Page 264)

7-14 SC140 DSP Core Reference Manual
Static Programming Rules
Example 7-20. Data Source Use of Nn and Mn Registers
move.l n0,d0 move.l n0,d1 ;not allowed
ift move.l n0,d0 iff move.l n0,d1 ;allowed
move.l n0,d0 move.l n1,d1 ;allowed
move.l n0,d0 suba n0,r0 ;allowed
move.l n0,d0 move.l (r0)+n0,d1 ;allowed
move.l n0,d0 move.l (r0+n0),d1 ;allowed
move.l (r0)+n0,d0 move.l (r1)+n0,d1 ;allowed
move.l (r0)+n0,d0 move.l (r1+n0),d1 ;allowed
move.l (r0+n0),d0 move.l (r1+n0),d1 ;allowed
move.l n0,d0 vsl.2f d1:d3,(r0)+n0;allowed
adda n0,n0 move.l (r0)+n0,d1 ;allowed
adda n0,n0 move.l (r0+n0),d1 ;allowed
Rule G.P.6
In a VLES having two IFc subgroups, each subgroup can have up to one AGU instruction and two DALU
instructions. Prefix instructions (IFc, LPMARKx, NOP, and ISAP instructions) are not counted for this
rule. However, if the core assembler adds implicit AGU instructions to support ISAP memory accesses and
register transfers, this rule does apply to these implicit AGU instructions. For more details on how this
works, see
Section 6.4, “ISAP Memory Access,” on page 6-60.
Note that the overall number of DALU instructions in the entire VLES is restricted by Section , “Rule
G.G.3,” .
Example 7-21. IFc Having Two Subgroups
ift add d0,d2,d3 iff move.w d3,(r4) move.w d4,($8) ;not allowed
ift move.w d3,(r4) iff add d0,d2 clr d4 ;allowed
ift move.l d2,(r1) iff add d3,d4 {isap_ins} ;allowed
Rule G.P.7
Up to two IFc subgroups (different conditions) can be grouped in a VLES. An IFc group or subgroup must
have at least one instruction. An IFA subgroup (if present) must be the last (in the assembly source order)
instructions in a VLES.
Example 7-22. IFA Subgroup Must Be Last Instructions
ift add d0,d1,d2 iff add d3,d4,d5
ift iff inc d0 ;not allowed
inc d0 ift add d0,d1,d2 ;not allowed
ifa inc d0 ift add d0,d1,d2 ;not allowed
ift add d0,d1,d2 ifa inc d0 ;allowed