Freescale Semiconductor StarCore SC140 - Manual (Page 26)

xxvi SC140 DSP Core Reference Manual
Revision History
RAS Return address register
RTOS Real-time operating system
SAn Start address register n
SF Signed fractional
SI Signed integer
SM Saturation mode
SoC System-on-chip
SP Stack pointer
SR Status register
T True bit
UI Unsigned integer
VBA Interrupt vector base address register
VLES Variable length execution set instruction grouping
XABA Data memory address bus A
XABB Data memory address bus B
XDBA Data memory data bus A
XDBB Data memory data bus B
Table 2. Revision History
Revision Date Description
4.0 31 Aug, 2004 Fourth release of SC140
4.1 20 Sep, 2005 Misc. corrections (restored missing IADDNC.W instruction)
Table 1. Abbreviations (Continued)
Abbreviation Description