Freescale Semiconductor StarCore SC140 - Manual (Page 333)

DSP Core Instruction Set
SC140 DSP Core Reference Manual A-19
A.2 Instructions
The following pages list all of the SC140 instructions and provide specific details about each instruction’s
operation and encoding.
A.2.1 Instruction Definition Layout
INST Description (type) INST
Instruction name, the same as in the mnemonic
Operation Assembler Syntax
The fields under this header describe the
operations carried out by the various forms The fields under this header illustrate the assembler syntax for
the various forms of this instruction. The field in curly brackets
of this instruction.
Description
The paragraphs under this header provide a detailed description of the various forms of this instruction.
Status and Conditions that Affect or are Changed by Instruction
The paragraphs under this header explain how status bits and condition codes affect the execution of the instruction
Example
(Optional section added when examples make the instruction definition clearer.)
(The instruction as it would be entered by a programmer.)
The first column of the example lists the registers or memory addresses affected in the example.
The third column illustrate those registers and memory locations AFTER execution takes place.
Instruction Formats and Opcodes
The fields under this header define the instruction:
Instruction
Words Cycles Type
Opcode
The instruction in assembler
syntax. One to three words (16 bits per word) of bits defining
the opcode as the core decodes it.
Number of words in memory
used by this instruction.
The number of cycles used in execution of this instruction. Addressing modes and the machine’s state
The instruction’s type relevant to non-prefix grouping. See
Instruction Fields
(Optional section added when the instruction has one or more operands.)
Each field shows how the operand appears in the Mnemonic and Opcode fields of the
Instruction Formats and Opcodes section. A field contains a table of registers or the definition
of an immediate value, an absolute address displacement/offset, or an absolute address.
A table of registers lists single register groups, register pair groups, address offset/post increment
definition groups, or register quad groups.
Instruction type
can affect the cycle count of instructions. See Section 5.3, "Instruction Timing" for more details.
Section 5.2.2.1, Serial Grouping, for details.
to the right of an instruction defines the range of a constant used
as an operand, and its alignment (B = byte, W = word,
L = long word/2 words, Q = quad word/4 words) if used
The second column illustrates those registers, immediates, and memory locations BEFORE execution takes place.
inst
as an address or in an address calculation.
and how the instruction affects clearing or setting particular condition codes and status bits.
The examples show the effects on the programmer’s model (registers and memory), and do not reflect the pipeline
timing of the updates.
(AGU, DALU, etc.)
A brief description of the instruction