Freescale Semiconductor StarCore SC140 - Manual (Page 328)

A-14 SC140 DSP Core Reference Manual
DSP Core Instruction Set
MPYR Multiply signed fractions and round
MPYSU Multiply signed fraction and unsigned fraction
MPYUS Multiply unsigned fraction and signed fraction
MPYUU Multiply unsigned fraction and unsigned fraction
NEG Negate
RND Round
SAT.F Saturate fractional value in data register to fit in high portion
SAT.L Saturate value in data register to fit in 32 bits
SBC Subtract long with carry
SBR Subtract and round
SUB Subtract
SUB2 Subtract two words
SUBL Shift left and subtract
SUBNC.W Subtract without changing the carry bit in the status register
TFR Transfer data register to a data register
TFRF Conditional data register transfer, if the T bit is clear
TFRT Conditional data register transfer, if the T bit is set
TSTEQ Test for equal to zero
TSTGE Test for greater than or equal to zero
TSTGT Test for greater than zero
Table A-8. DALU Logical Instructions (BFU)
Instruction Description
AND Logical AND
ASLL Multi-bit arithmetic shift left
ASLW Word arithmetic shift left (16 bit shift)
ASRR Multi-bit arithmetic shift right
ASRW Word arithmetic shift right (16 bit shift)
CLB Count leading bits (ones or zeros)
EOR Logical exclusive OR
EXTRACT Extract signed bit field
EXTRACTU Extract unsigned bit field
INSERT Insert bit field
LSLL Multi-bit logical shift left
LSR Logical shift right by one bit
LSRR Multi-bit logical shift right
LSRW Word logical shift right (16-bit shift)
NOT One’s complement (inversion)
OR Logical inclusive OR
Table A-7. DALU Arithmetic Instructions (MAC) (Continued)
Instruction Description