Freescale Semiconductor StarCore SC140 - Manual (Page 177)

Trace Unit Registers
SC140 DSP Core Reference Manual 4-67
In order to ensure that the LSB value of the trace data is always valid according to this convention, the
values of the 31-bit event counter and event counter extension are traced shifted one position to the left,
occupying positions [31:1] of the traced 32-bit value. Hence for example a counter value of 0x8 will be
traced as 0x10. The debugger SW should account for this shift when interpreting trace data.
When tracing in TEXEC mode, the LSB of the trace buffer entry is written with the valid T-bit value from
the SR. The value is potentially set by the previous execution set, which is the previous trace buffer entry.
The T bit value in a trace entry relates to the predicated DALU instructions (IFc on DALU instructions) in
the current execution set , and relates to the predicated AGU instructions (IFc on AGU instructions) in the
next execution set .
The tracing modes in the TB_CTRL register can only be changed when the trace buffer is disabled.
Tracing could be enabled again after no less than 5 VLES from when it has been disabled.
Figure 4-28 displays the bit configuration of TB_CTRL. Shaded areas are reserved.
Figure 4-28. Trace Buffer Control Register (TB_CTRL)
The TB_CTRL fields are described in the following table.
BITS 15-8 7 6 5 4 3 2 1 BIT 0
TCNTEXT TCOUNT TLOOP TEN TMARK TEXEC TINT TCHOF
TYPE rw rw rw rw rw rw rw rw rw
RESET 0 0 0 0 0 0 0 0 0
Table 4-23. TB_CTRL Description
Name Description Settings
TCNTEXT
Bit 7 Trace Buffer Extension Counter
Mode — Enables a special mode of the
trace unit where each destination
address put into the trace buffer is
followed by the value of the extension
counter register. 0 = Tracing of the extension counter is disabled
1 = Tracing of the extension counter is enabled
TCOUNT
Bit 6 Trace Buffer Counter Mode —
Enables a special mode of the trace unit
where each destination address put into
the trace buffer is followed by the value
of the event counter register. When both
counter mode bits (TCOUNT and
TCNTEXT) are set, the event counter
register is first written followed by the
extension counter register
.
0 = Tracing of the counter is disabled
1 = Tracing of the counter is enabled