Freescale Semiconductor StarCore SC140 - Manual (Page 31)

Core Architecture Features
SC140 DSP Core Reference Manual 1-5
Figure 1-1. Block Diagram of a Typical SoC Configuration with the SC140 Core
1.3.2 Variable Length Execution Set (VLES) Software Model
The VLES software model is the instruction grouping used by the SC140 to address the requirements of
DSP kernels. Using an orthogonal compiler-friendly instruction set, this model maintains a compact code
density for applications.
All SC140 instruction words are 16 bits wide. Most instructions are encoded with one word. Each SC140
instruction encodes an atomic (lowest-level) operation. For example, MAC and store (move) instructions
are encoded in 16 bits. Since atomic operations need fewer bits to encode, the 16-bit instruction set
becomes fully orthogonal and very rich in the functionality it supports.
In order to execute signal processing kernels, a set of SC140 instructions can be grouped to be executed in
parallel. The PSEQ performs this automatically with up to four DALU instructions and two AGU
instructions executed at the same time.
SC140 core
EOnCE ISAP
Instruction
cache
Data
cache
Unified M1
prog. & data
memory
SoC
SC140 platform
DSP expansion area
System expansion area
Bus switch & interfaces
RAM ROM
P
XA
XB
Trace
buffer
JT
AG
Standard I/O Peripherals
Application specific accelerators
General purpose programmable
accelerators
External memory interface
Level-2 caches
On-chip RAM and ROM
Host interface
Other micro-controllers
DMA
PLL
PIC