Freescale Semiconductor StarCore SC140 - Manual (Page 256)

7-6 SC140 DSP Core Reference Manual
Programming Rule Notation
7.4.7 AGU Arithmetic Instructions
“AGU arithmetic instructions” are those instructions that execute during the Address Generation pipeline
stage. This includes all instructions in
Table A-9: AGU Arithmetic Instructions on page A-15. All SC140
instructions in this category end with the letter A (such as CMPEQA, ADDA, TFRA) with the following
exceptions: IFA (a prefix instruction) and BRA (a non-loop COF instruction) are excluded.
7.4.8 Change-Of-Flow Destinations
A “change-of-flow (COF) destination” is any non-sequential change in the program counter (PC) register.
COF destinations can be caused by COF instructions, hardware loop LA to SA iterations, and exceptions.
Exceptions include instruction exceptions and hardware interrupts as described in
Section 5.8, “Exception
Processing.”
7.4.8.1 COF Instructions
A “COF instruction” specifies a (usually non-sequential) destination address that may implicitly write the
program counter (PC) register. The COF result may be conditional on the T bit. All references to “COF
instructions” in this manual include both the non-loop COF instructions listed in
Table A-13: AGU
Non-Loop Change-of-Flow Instructions on page A-17 and the loop COF instructions (BREAK, CONT,
CONTD, and SKIPLS) from Table A-14: AGU Loop Control (Including Loop COF) Instructions on page
A-18.
7.4.9 Delayed COF Instructions
A “delayed COF instruction” is a COF instruction that also executes the next sequential VLES. All COF
instructions in this category end with the letter D.
Example 7-2. Delayed COF Instructions
BFD
BRAD
BSRD
BTD
CONTD
JFD
JMPD
JSRD
JTD
RTED
RTSD
RTSTKD
7.4.9.1 Delay Slot
A “delay slot” is the next sequential VLES after a VLES having a “delayed COF instruction.”