Freescale Semiconductor StarCore SC140 - Manual (Page 80)

2-48 SC140 DSP Core Reference Manual
Address Generation Unit
Table 2-22 describes the modulo register Mj values and the corresponding multiple wrap-around address
calculation.
2.3.5 Arithmetic Instructions on Address Registers
The SC140 core provides arithmetic instructions on the address registers (R0–R15), offset registers
(N0–N3), the stack pointer (SP), and the program counter (PC).
Address modification modes can affect the arithmetic results stored in R0-R7 using instructions ADDA,
SUBA, ADDL1A, or ADDL2A. In addition, an address calculation that increments or decrements address
register R0-R7 is affected by the modifier mode. When updating R0-R7 in modulo addressing mode, the
modulo registers hold the modulus.
Table 2-23 lists the arithmetic instructions that are executed in the AGU unit. A more detailed description
of the operations is provided in
Appendix A, “SC140 DSP Core Instruction Set.”
Table 2-22. Modulo Register Values for Wrap-Around Modulo Addressing Mode
Modifier Mj Address Calculation Arithmetic
$0000 0001 Multiple Wrap-around Modulo 2
$0000 0003 Multiple Wrap-around Modulo 4
$0000 0007 Multiple Wrap-around Modulo 8
$7FFF FFFF
Multiple Wrap-around Modulo 2 31
$FFFF FFFF Linear
Table 2-23. AGU Arithmetic Instructions
Instruction Description
ADDA AGU Add (affected by the modifier mode)
ADDL2A AGU Add with 2-bit left shift of source operand (affected by the
modifier mode)
ADDL1A AGU Add with 1-bit left shift of source operand (affected by the
modifier mode)
ASL2A AGU Arithmetic shift left by 2 bits (32-bit)
ASLA AGU Arithmetic shift left (32-bit)
ASRA AGU Arithmetic shift right (32-bit)
CMPEQA AGU Compare for equal
CMPGTA AGU Compare for greater than
CMPHIA AGU Compare for higher (unsigned)
DECA AGU Decrement register (affected by the modifier mode)
DECEQA AGU Decrement and set T if result is zero