Freescale Semiconductor StarCore SC140 - Manual (Page 153)

EOnCE Controller Registers
SC140 DSP Core Reference Manual 4-43
4.7.4 EOnCE Receive Register (ERCV)
ERCV is a 64-bit shift register that can be written from the TDI input signal. The register can be read by
the software as two 32-bit registers. The ERCV register has to be read in a specific order with the Least
Significant Part first. The Least Significant Part read is optional, but the Most Significant Part read is
required to clear the RCV bit in the ESR.
ERCV is used to transfer data from the host. This can be done in the following sequence:
1. The host issues a write command to the ERCV register.
2. The host transmits 64 bits through TDI into the ERCV register.
3. The RCV bit in the ESR is set by the EOnCE.
4. If the RCVINT bit in the EMCR is set, the core is interrupted by a debug exception.
Otherwise, the core must poll the RCV status bit to know when the data is ready in the
ERCV register.
5. The core reads the ERCV register using move instructions.
6. The RCV bit in ESR is cleared by EOnCE. The EE3 signal can be programmed to reflect the
value of the RCV bit, informing the host when further data can be transmitted.
4.7.5 EOnCE Transmit Register (ETRSMT)
ETRSMT is a 64-bit shift register that can be read by the TDO output signal. The register can be written by
software as two 32-bit registers. The ETRSMT register must be written in a specific order, with the Least
Significant Part first. The Least Significant Part write is optional, but the Most Significant Part write is
required to set the TRSMT status bit.
The ETRSMT register can transmit data from the core to an external host while the core is running. This
can be done in the following sequence:
1. The core writes data to be transmitted into the ETRSMT register.
2. The TRSMT bit in the ESR is set automatically by the EOnCE.
3. The host polls the TRSMT bit in the ESR to detect that the data in the ETRSMT register is
available. Alternatively, the host can program the EE4 signal to be set when the TRSMT bit
is set.
4. The host issues a read command to the ETRSMT register and reads the register serially
through the TDO line.
5. The TRSMT bit is cleared on completion of the read by the host debugger. If the TRSINT
bit in the EMCR is set, the core is interrupted by a debug exception, informing the core that
further data can be transmitted.