Freescale Semiconductor StarCore SC140 - Manual (Page 311)

NOP Definition
SC140 DSP Core Reference Manual 7-61
5. Source syntax order in a VLES generally has no effect on the baseline size, as parallel
semantics define no instruction serialization within a VLES. The baseline size is determined
by the encoding rules in the assembler. There are two cases where source order matters for
the programmer - 1) for multiple conditional subgroups in a VLES, any IFA subgroup must
be the last (right-most) subgroup in the source syntax, and 2) if multiple instructions in the
same VLES affect SR[C], the last (right-most) instruction in the source syntax that actually
executes updates SR[C]. This source order syntax affects the encoding order of the VLES
and can affect the baseline size, but not the size increase due to NOPs in the source VLES.
6. Conditional (IFc) syntax requires special rules to provide deterministic NOP word padding
when the two subgroups are used. If a conditional group or subgroup contains only NOPs,
it should be assembler mapped as follows (a colon “:” is the concatenation operation):
IFT NOP --> IFT (prefix ccc=010):NOP
IFF NOP --> IFF (prefix ccc=011):NOP
IFT NOP IFA subgroup2 --> IFA (prefix ccc=000) group2:NOP (same as group2:NOP)
IFF NOP IFA subgroup2 --> IFA (prefix ccc=000) group2:NOP (same as group2:NOP)
IFT subgroup1 IFA NOP --> IFT (prefix ccc=010) group1:NOP
IFF subgroup1 IFA NOP --> IFF (prefix ccc=011) group1:NOP
IFT subgroup1 IFF NOP --> IFT (prefix ccc=010) group1:NOP
IFT NOP IFF subgroup2 --> IFF (prefix ccc=011) group2:NOP
This mapping converts each NOP-only conditional group or subgroup to embedded NOPs
concatenated with a conditional group (no subgroups). This is necessary to ensure that each NOP
adds exactly one word to the baseline size. Some of these are not useful cases, but are legal source
syntax for the assembler.
If a conditional group or subgroup has a NOP with other instructions, the NOPs should ignore their
subgroup when concatenating with the baseline VLES encoding. In other word, NOP padding can
be added to either subgroup as shown in the examples.
7. The FALIGN assembler directive should assemble the VLES source code including existing
source NOPs, determine the VLES address boundaries, and add the minimum number of
PADs to achieve the desired fetch address alignment. The assembler can spread PADs across
several VLES (including conditional VLES) to avoid a cycle penalty, or add them as a
standalone VLES if the alignment cannot be achieved without a cycle penalty.
7.9.1 Grouping Examples
Assume there are N NOP instructions in the source VLES (including PADs added by the FALIGN
directive).
1. If a baseline VLES does not require a prefix, the first source NOP is encoded as a 1W VLES
prefix. For example:
[INC D0NOP]
is encoded as:
[1W prefix, INC]
and