Freescale Semiconductor MCF5480 - Manual (Page 113)

Programming Model
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 3-9
3.3.1 User Programming Model
The user programming model, shown in Figure 3-3 , consists of the following registers:
• 16 general-purpose, 32-bit registers (D7–D0 and A7–A0); A7 is a user stack pointer
• 32-bit program counter
• 8-bit condition code register
• Registers to support the EMAC
• Register to support the floating-point unit (FPU)
3.3.1.1 Data Registers (D0–D7)
Registers D0–D7 are used as data registers for bit, byte (8-bit), word (16-bit), and longword (32-bit)
operations. They may also be used as index registers.
3.3.1.2 Address Registers (A0–A6)
The address registers (A0–A6) can be used as software stack pointers, index registers, or base address
registers, and may be used for word and longword operations.
3.3.2 User Stack Pointer (A7)
The CF4e architecture supports two unique stack pointer (A7) registers—the supervisor stack pointer
(SSP) and the user stack pointer (USP). This support provides the required isolation between operating
modes as dictated by the virtual memory management scheme provided by the memory management unit
(MMU). The SSP is described in Section 5.4.2, “Supervisor/User Stack Pointers .”
3.3.2.1 Program Counter (PC)
The PC holds the address of the executing instruction. For sequential instructions, the processor
automatically increments PC. When program flow changes, the PC is updated with the target instruction.
For some instructions, the PC specifies the base address for PC-relative operand addressing modes.
3.3.2.2 Condition Code Register (CCR)
The CCR, Figure 3-4 , occupies SR[7–0], as shown in Figure 3-3 . The CCR[4–0] bits are indicator flags
based on results generated by arithmetic operations.
7 6 5 4 3 2 1 0
R 0 0 0 X N Z V C
W
Reset 0 0 0 0 0 0 0 0
Reg
Addr
Accessed using R/W commands for the status register
Figure 3-4. Condition Code Register (CCR)