Freescale Semiconductor MCF5480 - Manual (Page 185)

MMU Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 5-19
5.5.5 MMU Operation
The processor sends instruction fetch requests and data read/write requests to the MMU in the instruction
and operand address generation cycles (IAG and OAG). The controller and memories occupy the next two
pipeline stages, instruction fetch cycles 1 and 2 (IC1 and IC2) and operand fetch cycles 1 and 2 (OC1 and
OC2). For late writes, optional data pipeline stages are added to the controller as well as any writable
memories.
Table 5-11 shows the association between memory pipeline stages and the processor’s pipeline structures,
shown in Figure 5-1 .
.
Version 4 use the same 2-cycle read pipeline developed for Version 3. Each has 32-bit address and 32-bit
read data paths. Version 4 uses synchronous memory elements for all memory control units. To support
this, certain control information and all address bits are sent on the at the end of the cycle before the initial
bus access cycle (The data has an additional 32-bit write data path). For processor store operations,
Version 4 ColdFire uses a late-write strategy, which can require 2 additional data cycles. This strategy
yields the pipeline behavior described in Table 5-12 .
The contains two independent memory unit access controllers and two independent controllers. Each
instruction and data is analyzed to see which, if any, controller is referenced. This information, along with
cache mode, store precision, and fault information, is sourced during KC1.
The optional MMU is referenced concurrently with the memory unit access controllers. It has two
independent control sections to simultaneously process an instruction and data request. Figure 5-1 shows
how the MMU and memory unit access controllers fit in the pipeline. As the diagram shows, core address
and attributes are used to access the mapping registers and the MMU. By the middle of the KC1 cycle, the
memory address is available along with its corresponding access control.
Table 5-11. Version 4 Memory Pipelines
Memory Pipeline Stage Instruction Fetch Pipeline Operand Execution Pipeline
J stage IAG OAG
KC1 stage IC1 OC1
KC2 stage IC2 OC2
Operand execute stage n/a EX
Late-write stage n/a DA
Table 5-12. Pipeline Cycles
Cycle Description
J Control and partial address broadcast (to start synchronous memories)
KC1 Complete address and control broadcast plus MMU information. It is during this cycle that all memory
element read operations are performed; that is, memory arrays are accessed.
KC2 Select appropriate memory as source, return data to processor, handle cache misses or hold pipeline
as needed.
EX Optional write stage, pipeline address and control for store operations.
DA Data available for stores from processor; memory element update occurs in the next cycle.