Freescale Semiconductor MCF5480 - Manual (Page 280)

MCF548x Reference Manual, Rev. 3
8-30 Freescale Semiconductor
8.5.2 BDM Serial Interface
When the CPU is halted and PSTDDATA reflects the halt status, the development system can send
unrestricted commands to the debug module. The debug module implements a synchronous protocol using
two inputs (DSCLK and DSI) and one output (DSO), where DSO is specified as a delay relative to the
rising edge of the processor clock. See Table 8-1 . The development system serves as the serial
communication channel master and must generate DSCLK.
The serial channel operates at a frequency from DC to 1/5 of the PSTCLK frequency. The channel uses
full-duplex mode, where data is sent and received simultaneously by both master and slave devices. The
transmission consists of 17-bit packets composed of a status/control bit and a 16-bit data word. As shown
in Figure 8-18 , all state transitions are enabled on a rising edge of the PSTCLK clock when DSCLK is
high; that is, DSI is sampled and DSO is driven.
Figure 8-18. Maximum BDM Serial Interface Timing
DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled, along
with DSI, on the rising edge of PSTCLK. DSO is delayed from the DSCLK-enabled PSTCLK rising edge
(registered after a BDM state machine state change). All events in the debug module’s serial state machine
are based on the PSTCLK rising edge. DSCLK must also be sampled low (on a positive edge of PSTCLK)
between each bit exchange. The msb is sent first. Because DSO changes state based on an internally
recognized rising edge of DSCLK, DSO cannot be used to indicate the start of a serial transfer. The
development system must count clock cycles in a given transfer. C0–C4 are described as follows:
• C0: Set the state of the DSI bit.
• C1: First synchronization cycle for DSI (DSCLK is high).
• C2: Second synchronization cycle for DSI (DSCLK is high).
• C3: BDM state machine changes state depending upon DSI and whether the entire input data
transfer has been transmitted.
• C4: DSO changes to next value.
NOTE
A not-ready response can be ignored except during a memory-referencing
cycle. Otherwise, the debug module can accept a new serial transfer after 32
processor clock periods.
8.5.2.1 Receive Packet Format
The basic receive packet, Figure 8-19 , consists of 16 data bits and 1 status bit
PSTCLK
DSCLK
Next State
BDM State
Machine
DSO
DSI
Current State
Current Next
Past Current
C1 C2 C3 C4 C0