Freescale Semiconductor MCF5480 - Manual (Page 354)

MCF548x Reference Manual, Rev. 3
13-2 Freescale Semiconductor
and status register data, along with the 32-bit program counter value of the instruction that was interrupted
(see Section 3.8.1, “Exception Stack Frame Definition,” for more information on the stack frame format).
After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer from the
exception vector table using the vector number as the offset, and then jumps to that address to begin
execution of the service routine.
After the status register is stored in the exception stack frame, the SR[I] mask field is set to the level of the
interrupt being acknowledged, effectively masking that level and all lower values while in the service
routine. For many peripheral devices, the processing of the IACK cycle directly negates the interrupt
request, while other devices require that request to be explicitly negated during the processing of the
service routine.
For the MCF548x, the processing of the interrupt acknowledge cycle is fundamentally different than
previous 68K/ColdFire cores. In the new approach, all IACK cycles are directly handled by the interrupt
controller, so the requesting peripheral device is not accessed during the IACK. As a result, the interrupt
request must be explicitly cleared in the peripheral during the interrupt service routine. For more
information, see Section 13.1.1.1.3, “Interrupt Vector Determination .”
Unlike the M68000 family, all ColdFire processors guarantee that the first instruction of the service routine
is executed before sampling for interrupts is resumed. By making this initial instruction a load of the SR,
interrupts can be safely disabled, if required.
During the execution of the service routine, the appropriate actions must be performed on the peripheral
to negate the interrupt request.
For more information on exception processing, see the ColdFire Programmer’s Reference Manual at
http://www.freescale.com/coldfire
13.1.1.1 Interrupt Controller Theory of Operation
To support the interrupt architecture of the 68K/ColdFire programming model, the combined 63 interrupt
sources are organized as 7 levels, with each level supporting up to nine prioritized requests. Consider the
priority structure within a single interrupt level (from highest to lowest priority) as shown in Table 13-1 .
The level and priority is fully programmable for all sources except interrupt sources 1–7. Interrupt source
1–7 (the external interrupts) are fixed at the corresponding level’s midpoint priority. Thus, a maximum of
Table 13-1. Interrupt Priority Within a Level
ICR[2:0] Priority
Interrupt
Sources
111 7 (Highest) 8-63
110 6 8-63
101 5 8-63
100 4 8-63
— Fixed Midpoint Priority 1-7
011 3 8-63
010 2 8-63
001 1 8-63
000 0 (Lowest) 8-63