Freescale Semiconductor MCF5480 - Manual (Page 384)

MCF548x Reference Manual, Rev. 3
15-12 Freescale Semiconductor
Most PDDR_x registers have a full 8-bit implementation, as shown in Figure 15-7 . The remaining
PDDR_x registers use fewer than eight bits. Their bit definitions are shown in Figure 15-8 , Figure 15-9 ,
Figure 15-10 , and Figure 15-11 .
The PDDR_x registers are read/write. At reset, all bits in the PDDR_x registers are cleared. Setting any bit
in a PDDR_x register configures the corresponding port x pin as an output. Clearing any bit in a PDDR_x
register configures the corresponding pin as an input.
15.3.2.2.1 8-Bit PDDR_x Registers
The 8-bit PDDR_x registers include the following:
• PDDR_FBCTL
• PDDR_FEC0H
• PDDR_FEC0L
• PDDR_FEC1H
• PDDR_FEC1L
• PDDR_PSC3PSC2
• PDDR_PSC1PSC0
Figure 15-7 displays the 8-bit PDDR_x registers.
15.3.2.2.2 7-Bit PDDR_x Register
The 7-bit PDDR_DSPI register sets the data direction for the PDSPIn port. Figure 15-8 displays the 7-bit
PDDR_DSPI register.
7 6 5 4 3 2 1 0
R DDx7 DDx6 DDx5 DDx4 DDx3 DDx2 DDx1 DDx0
W
Reset 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0xA10 (PDDR_FBCTL), 0xA14 (PDDR_FEC0H), 0xA15 (PDDR_FEC0L), 0xA16 (PDDR_FEC1H), 0xA17
(PDDR_FEC1L), 0xA1C (PDDR_PSC3PSC2), 0xA1D (PDDR_PSC1PSC0)
Figure 15-7. 8-Bit Port Data Direction Registers
Table 15-9. 8-Bit PDDR_x Field Descriptions
Bits Name Description
7–0 DDxn PDDR_x Data Direction Bits
0 PORT x pin is configured as input
1 PORT x pin is configured as output