Freescale Semiconductor MCF5480 - Manual (Page 385)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 15-13
15.3.2.2.3 5-Bit PDDR_x Registers
The 5-bit PDDR_x registers are the data direction registers for PPCIBGn (PDDR_PCIBG) and PPCIBRn
(PDDR_PCIBR). Figure 15-9 displays the 5-bit PDDR_x registers.
15.3.2.2.4 4-Bit PDDR_x Registers
The 4-bit PDDR_x registers are for data direction of PDMAn (PDDR_DMA) and PFECI2Cn
(PDDR_FECI2C). Figure 15-10 displays the 4-bit PDDR_x registers.
7 6 5 4 3 2 1 0
R 0 DDDSP
6
DDDSP5 DDDSP4 DDDSPI3 DDDSPI2 DDDSP1 DDDSP0
W
Reset 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0xA1E (PDDR_DSPI)
Figure 15-8. 7-Bit PDDR_DSPI Data Direction Register
Table 15-10. 7-Bit PDDR_DSPI Field Descriptions
Bits Name Description
7 — Reserved, should be cleared
6–0 DDDSPn PODR_DSPI data direction
0 PDSPIn pin configured as input
1 PDSPIn pin configured as output
7 6 5 4 3 2 1 0
R 0 0 0 DDx4 DDx3 DDx2 DDx1 DDx0
W
Reset 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0xA11 (PDDR_FBCS), 0xA19 (PDDR_PCIBG), 0xA1A (PDDR_PCIBR)
Figure 15-9. 5-Bit PDDR_PCIBG and PDDR_PCIBR Registers
Table 15-11. 5-Bit PDDR_PCIBG and PDDR_PCIBR Field Descriptions
Bits Name Description
7–5 — Reserved, should be cleared
4–0 DDxn PDDR_PCIBG and PDDR_PCIBR Data Direction
0 PPCIBGn or PPCIBRn pin is configured as input
1 PPCIBGn or PPCIBRn pin is configured as output