Freescale Semiconductor MCF5480 - Manual (Page 422)

MCF548x Reference Manual, Rev. 3
17-6 Freescale Semiconductor
17.5 Chip-Select Operation
Each chip-select has a dedicated set of the following registers for configuration and control:
• Chip-select address registers (CSARn) control the base address space of the chip-select. See
Section 17.5.2.1, “Chip-Select Address Registers (CSAR0–CSAR5).”
• Chip-select mask registers (CSMRn) provide 16-bit address masking and access control. See
Section 17.5.2.2, “Chip-Select Mask Registers (CSMR0–CSMR5).”
• Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state
generation, address setup and hold times, and automatic acknowledge generation features. See
Section 17.5.2.3, “Chip-Select Control Registers (CSCR0–CSCR5).”
FBCS0 is a global chip-select after reset and provides re-locatable boot ROM capability.
17.5.1 General Chip-Select Operation
When a bus cycle is initiated, the MCF548x first compares its address with the base address and mask
configurations programmed for chip-selects 0–5 (configured in CSCR0–CSCR5). If the driven address
matches a programmed chip-select, the appropriate chip-select is asserted fulfilling the requirements as
programmed in the respective configuration register.
17.5.1.1 8-, 16-, and 32-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. See Section 17.5.2.3,
“Chip-Select Control Registers (CSCR0–CSCR5) .” Note that the MCF548x always drives 32-bit address
on the AD bus in the first cycle regardless of the external device’s address size. The external device must
connect its address lines to the appropriate AD bits starting from AD0 and upward. It must also connect
its data lines to the AD bus starting from the AD31 and downward. No bit ordering is required when
connecting address and data lines to the AD bus. For example, a 16-bit address/16-bit data device would
connect its addr[15:0] to AD[15:0] and data[15:0] to AD[31:16]. See Figure 17-6 for graphical connection.
17.5.1.2 Global Chip-Select Operation
FBCS0, the global (boot) chip-select, allows address decoding for boot ROM before system initialization.
Its operation differs from other external chip-select outputs after system reset.
After system reset, FBCS0 is asserted for every external access. No other chip-select can be used until the
valid bit, CSMR0[V], is set, at which point FBCS0 functions as configured. After this, FBCS[5:1] can be
used as well. At reset, the port size, and automatic acknowledge functions of the global chip-select are
determined by the logic levels on the AD[2:0] signals. Table 17-3 , Table 17-4 , and Table 17-5 list the
various reset encodings for the configuration signals.
Table 17-3. AD4/FB_CONFIG Selection of Non-Multiplexed
32-bit Address/32-bit Data Mode
AD4 FlexBus Operating Mode
0 AD[31:0] used for data.
PCIAD[31:0] used for address
1
1
If the non-multiplexed 32-bit address/32-bit data mode is selected the PCI bus
cannot be used.
1 PCIAD[31:0] used for PCI bus.
AD[31:0] used for both address and data.