Freescale Semiconductor MCF5480 - Manual (Page 710)

MCF548x Reference Manual, Rev. 3
23-2 Freescale Semiconductor
23.1.2 Features
The basic features of the JTAG module are the following:
• Performs boundary-scan operations to test circuit board electrical continuity
• Bypasses instruction to reduce the shift register path to a single cell
• Sets chip output pins to safety states while executing the bypass instruction
• Samples the system pins during operation and transparently shift out the result
• Selects between JTAG TAP controller and Background Debug Module (BDM) using the
MTMOD0 pin
23.1.3 Modes of Operation
The MTMOD0 pin can select between the following modes of operation:
• JTAG mode
• BDM—background debug mode (For more information, refer to Chapter 8, “Debug Support.” )
23.2 External Signal Description
The JTAG module has five input and one output external signals, as described in Table 23-1 .
23.2.1 Detailed Signal Description
23.2.1.1 Test Mode 0 (MTMOD0)
The MTMOD0 pin selects between Debug module and JTAG. If MTMOD0 is low, the Debug module is
selected; if it is high, the JTAG is selected. Table 23-2 summarizes the pin function selected depending
upon MTMOD0 logic state.
Table 23-1. Signal Properties
Name Direction Function Reset State Pull up
MTMOD0 Input JTAG/BDM selector input — —
TCK Input JTAG Test clock input — Active
TMS/BKPT Input JTAG Test mode select / BDM Breakpoint — Active
TDI/DSI Input JTAG Test data input / BDM Development serial input — Active
TRST/DSCLK Input JTAG Test reset input / BDM Development serial clock — Active
TDO/DSO Output JTAG Test data output / BDM Development serial output Hi-Z / 0 —