Freescale Semiconductor MCF5480 - Manual (Page 934)

MCF548x Reference Manual, Rev. 3
30-4 Freescale Semiconductor
transceiver via this interface in the following sections: Section 30.4.3, “Network Interface Options ,”
Section 30.4.13, “MII Data Frame ,” and Section 30.4.14, “MII Management Frame Structure .”
30.1.5.2.2 10 Mpbs 7-Wire Interface Operation
The FEC supports a 7-wire interface as used by many 10 Mbps Ethernet transceivers. The
RCR[MII_MODE] bit controls this functionality. If this bit is deasserted, the MII mode is disabled and the
10 Mbps, 7-wire mode is enabled.
30.1.5.3 Address Recognition Options
The address options supported are promiscuous, broadcast reject, individual address (hash or exact match),
and multicast hash match. Address recognition options are discussed in detail in Section 30.4.6, “Ethernet
Address Recognition ”.
30.1.5.4 Internal Loopback
Internal loopback mode is selected via RCR[LOOP]. Loopback mode is discussed in detail in
Section 30.4.11, “Internal and External Loopback ”.
30.2 External Signals
The MII interface consists of 18 signals. The transmit and receive functions require seven signals each,
four data signals, a delimiter, error, and clock. In addition, there are two signals which indicate the status
of the media, one indicates the presence of a carrier, and the second one indicates that a collision has
occurred. The remaining two signals provide a management interface. Each MII signal is described below.
30.2.1 Transmit Clock (EnTXCLK)
EnTXCLK is a continuous input clock that provides a timing reference for EnTXEN, EnTXD, and
EnTXER.
30.2.2 Receive Clock (EnRXCLK)
EnRXCLK is a continuous input clock which provides a timing reference for EnRXDV, EnRXD, and
EnRXER.
30.2.3 Transmit Enable (EnTXEN)
Assertion of this output signal indicates that there are valid nibbles being presented on the MII. This signal
is asserted with the first nibble of preamble and is negated prior to the first EnTXCLK following the final
nibble of the frame.
30.2.4 Transmit Data[3:0] (EnTXD[3:0])
EnTXD[3:0] represent a nibble of data when EnTXEN is asserted and have no meaning when EnTXEN is
de-asserted. EnTXD0 is used for serial data in 7-wire mode. Table 30-2 summarizes the permissible
encoding of EnTXD.