Freescale Semiconductor MCF5480 - Manual (Page 116)

MCF548x Reference Manual, Rev. 3
3-12 Freescale Semiconductor
3.3.5.1 Status Register (SR)
The SR stores the processor status, the interrupt priority mask, and other control bits. Supervisor software
can read or write the entire SR; user software can read or write only SR[7–0], described in Section 3.3.2.2,
“Condition Code Register (CCR) .” The control bits indicate processor states—trace mode (T), supervisor
or user mode (S), and master or interrupt state (M). SR is set to 0x27xx after reset.
Table 3-3 describes SR fields.
3.3.5.2 Vector Base Register (VBR)
The VBR holds the base address of the exception vector table in memory. The displacement of an
exception vector is added to the value in this register to access the vector table. The VBR[19–0] bits are
not implemented and are assumed to be zero, forcing the vector table to be aligned on a 0-modulo-1-Mbyte
boundary.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
System byte Condition code register (CCR)
R T 0 S M 0 I 0 0 0 X N Z V C
W
Reset 0 0 1 0 0 1 1 1 0 0 0 — — — — —
Reg
Addr
0x27xx
Figure 3-7. Status Register (SR)
Table 3-3. SR Field Descriptions
Bits Name Description
15 T Trace enable. When T is set, the processor performs a trace exception after every
instruction.
13 S Supervisor/user state. Indicates whether the processor is in supervisor or user mode
0 User mode
1 Supervisor mode
12 M Master/interrupt state. Cleared by an interrupt exception. It can be set by software during
execution of the RTE or move to SR instructions so the OS can emulate an interrupt stack
pointer.
10–8 I Interrupt priority mask. Defines the current interrupt priority. Interrupt requests are inhibited
for all priority levels less than or equal to the current priority, except the edge-sensitive
level-7 request, which cannot be masked.
7–0 CCR Condition code register. See Table 3-1 .