Freescale Semiconductor MCF5480 - Manual (Page 315)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor i
Part II
System Integration Unit
Part II describes the system integration unit, which provides overall control of the bus and serves as the
interface between the ColdFire core processor complex and internal peripheral devices. It includes a
general description of the SIU and individual chapters that describe components of the SIU, such as the
interrupt controller, general purpose timers, slice timers, and GPIOs.
Contents
Part II contains the following chapters:
• Chapter 9, “System Integration Unit (SIU),” describes the SIU programming model, bus
arbitration, and system-protection functions for the MCF548x.
• Chapter 10, “Internal Clocks and Bus Architecture,” describes the clocking and internal buses of
the MCF548x and discusses the main functional blocks controlling the XL bus and the XL bus
arbiter
• Chapter 11, “General Purpose Timers (GPT),” describes the functionality of the four general
purpose timers, GPT0–GPT3.
• Chapter 12, “Slice Timers (SLT),” describes the two slice timers, shorter term periodic interrupts,
used in the MCF548x.
• Chapter 13, “Interrupt Controller,” describes operation of the interrupt controller portion of the
SIU. It includes descriptions of the registers in the interrupt controller memory map and the
interrupt priority scheme.
• Chapter 14, “Edge Port Module (EPORT),” describes EPORT module functionality.
• Chapter 15, “GPIO,” describes the operation and programming model of the parallel port pin
assignment, direction-control, and data registers.