Freescale Semiconductor MCF5480 - Manual (Page 843)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 27-25
27.7.4 Transfer Formats
The SPI serial communication is controlled by the serial communications clock (DSPISCK) signal and the
DSPICSn signals. The DSPISCK signal provided by the master device synchronizes shifting and sampling
of the data on the DSPISIN and DSPISOUT pins. The DSPICSn signals serve as enable signals for the
slave devices.
When the DSPI is the bus master, the CPOL and CPHA bits in the DSPI clock and transfer attributes
registers (DCTARn) select the polarity and phase of the clock. The polarity bit selects the idle state of
DSPISCK. The clock phase bit selects if the data on DSPISOUT is valid before or on the first DSPISCK
edge.
When the DSPI is the bus slave, CPOL and CPHA bits in the DCTAR0 select the polarity and phase of the
serial clock. Even though the bus slave does not control the DSPISCK signal, the clock polarity, clock
phase, and number of bits to transfer settings for both the master and slave must be identical to ensure
proper transmission.
The DSPI supports four different transfer formats:
• Classic SPI with CPHA = 0
• Classic SPI with CPHA = 1
• Modified transfer format with CPHA = 0
• Modified transfer format with CPHA = 1
A modified transfer format is supported to allow for high-speed communication with peripherals that
require longer setup times. The DSPI can sample the incoming data later than halfway through the cycle
to give the peripheral more setup time. The DMCR[MTFE] bit selects between classic SPI format and
modified transfer format. The modified transfer formats are described in Section 27.7.4.3, “Modified SPI
Transfer Format (MTFE = 1, CPHA = 0) ” and Section 27.7.4.4, “Modified SPI Transfer Format (MTFE =
1, CPHA = 1) .”
The classic SPI formats are described in Section 27.7.4.1, “Classic SPI Transfer Format (CPHA = 0) ” and
Section 27.7.4.2, “Classic SPI Transfer Format (CPHA = 1) .”
The DSPI provides the option of keeping the DSPICSn signals asserted between frames. See
Section 27.7.4.5, “Continuous Selection Format ” for details.
27.7.4.1 Classic SPI Transfer Format (CPHA = 0)
The transfer format shown in Figure 27-15 is used to communicate with peripheral SPI slave devices
where the first data bit is available on the first clock edge. In this format, the master and slave sample their
DSPISIN pins on the odd-numbered DSPISCK edges and change the data on their DSPISOUT pins on the
even-numbered DSPISCK edges.