Lenze EVS9332xP - Manual (Page 41)

Function library
Working with function blocks
3.1.4 Entries into the processing table
3−13
l
EDSVS9332P−EXT DE 2.0
Structure of the processing table for the configuration example Fig. 3−5:
1. DIGIN does not have to be entered into the processing table.
2. The first FB is AND1, since it receives its input signals from DIGIN and only has successors.
3. The second FB is OR1, since its signal source is the output of AND1 (predecessor). Hence, the
output signal in AND1 must be generated first, before being processed in OR1. At the same
time, OR1 has a successor. Hence, OR1 must be entered into the processing table before the
successor.
4. The third FB is AND2, since it has a predecessor (see 3.)
5. The entries under C0465 are as follows:
– Position 10: AND1 10500
– Position 11: OR1 10550
– Position 12: AND2 10505
This example was started with position 10, since these positions are not assigned in the default
setting.
FBs do not have to be entered into the processing table directly one after the other. Empty positions
in the processing table are permissible.
)
Note!
It is also possible that other FBs are entered between the FBs listed in the example.
FBs, which do not have to be entered into the processing table
The following signal sources are always executed and therefore do not need to be entered into the
processing table:
l AIF−IN
l CANx−IN
l DIGIN
l DIGOUT
l FCODE (all free codes)
l MCTRL
l fixed signal sources (FIXED0, FIXED0%, etc.)
Frequent errors
Malfunction Cause Remedy
FB does not supply an output signal FB was not entered into the processing table
C0465 Enter FB
FB only supplies constant signals FB was deleted from or overwritten in the
processing table C0465 Enter FB again, possibly under a different
subcode (list position)
The output signal does not arrive at the
following FB The connection between the FBs has not been
established Establish the connection (from the view of the
following FB) via the configuration code (CFG)
FB cannot be entered into the table C0465 Residual processing time is too short
(see C0466) Delete unused FBs (e. g. inputs and outputs
not used)
In networked drives, functions may be
assigned to other controllers
The drive controller transmits internally
calculated signals with a delay to the outputs. The FBs are processed in an incorrect
sequence Adapt the processing table under C0465 to the
signal flow