Document Outline

• SC140 DSP Core Reference Manual
• Chapter1 Introduction
  • 1.1 Target Markets
  • 1.2 Architectural Differentiation
  • 1.3 Core Architecture Features
    • 1.3.1 Typical System-On-Chip Configuration
    • 1.3.2 Variable Length Execution Set (VLES) Software Model
• Chapter2 Core Architecture
  • 2.1 Architecture Overview
    • 2.1.1 Data Arithmetic Logic Unit (DALU)
      • 2.1.1.1 Data Register File
      • 2.1.1.2 Multiply-Accumulate (MAC) Unit
      • 2.1.1.3 Bit-Field Unit (BFU)
      • 2.1.1.4 Shifter/Limiters
    • 2.1.2 Address Generation Unit (AGU)
      • 2.1.2.1 Stack Pointer Registers
      • 2.1.2.2 Bit Mask Unit (BMU)
    • 2.1.3 Program Sequencer Unit (PSEQ)
    • 2.1.4 Enhanced On-Chip Emulator (EOnCE)
    • 2.1.5 Instruction Set Accelerator Plug-in (ISAP) Interface
    • 2.1.6 Memory Interface
  • 2.2 DALU
    • 2.2.1 DALU Architecture
      • 2.2.1.1 Data Registers (D0–D15)
      • 2.2.1.2 Multiply-Accumulate (MAC) Unit
      • 2.2.1.3 Bit-Field Unit (BFU)
      • 2.2.1.4 Data Shifter/Limiter
      • 2.2.1.5 Scaling
      • 2.2.1.6 Limiting
      • 2.2.1.7 Scaling and Arithmetic Saturation Mode Interactions
    • 2.2.2 DALU Arithmetic and Rounding
      • 2.2.2.1 Data Representation
      • 2.2.2.2 Data Formats
      • 2.2.2.3 Multiplication
      • 2.2.2.4 Division
      • 2.2.2.5 Unsigned Arithmetic
      • 2.2.2.6 Rounding Modes
      • 2.2.2.7 Arithmetic Saturation Mode
      • 2.2.2.8 Multi-Precision Arithmetic Support
      • 2.2.2.9 Viterbi Decoding Support
  • 2.3 Address Generation Unit
    • 2.3.1 AGU Architecture
    • 2.3.2 AGU Programming Model
      • 2.3.2.1 Address Registers (R0–R15)
      • 2.3.2.2 Stack Pointer Registers (NSP, ESP)
      • 2.3.2.3 Offset Registers (N0–N3)
      • 2.3.2.4 Base Address Registers (B0–B7)
      • 2.3.2.5 Modifier Registers (M0–M3)
      • 2.3.2.6 Modifier Control Register (MCTL)
    • 2.3.3 Addressing Modes
      • 2.3.3.1 Register Direct Modes
      • 2.3.3.2 Address Register Indirect Modes
      • 2.3.3.3 PC Relative Mode
      • 2.3.3.4 Special Addressing Modes
      • 2.3.3.5 Memory Access Width
      • 2.3.3.6 Memory Access Misalignment
      • 2.3.3.7 Addressing Modes Summary
    • 2.3.4 Address Modifier Modes
      • 2.3.4.1 Linear Addressing Mode
      • 2.3.4.2 Reverse-carry Addressing Mode
      • 2.3.4.3 Modulo Addressing Mode
      • 2.3.4.4 Multiple Wrap-Around Modulo Addressing Mode
    • 2.3.5 Arithmetic Instructions on Address Registers
    • 2.3.6 Bit Mask Instructions
      • 2.3.6.1 Bit Mask Test and Set (Semaphore Support) Instruction
      • 2.3.6.2 Semaphore Hardware Implementation
    • 2.3.7 Move Instructions
  • 2.4 Memory Interface
    • 2.4.1 SC140 Endian Support
      • 2.4.1.1 SC140 Bus Structure
      • 2.4.1.2 Memory Organization
      • 2.4.1.3 Data Moves
      • 2.4.1.4 Multi-Register Moves
      • 2.4.1.5 Instruction Word Transfers
      • 2.4.1.6 Memory Access Behavior in Big/Little Endian Modes
• Chapter3 Control Registers
  • 3.1 Core Control Registers
    • 3.1.1 Status Register (SR)
    • 3.1.2 Exception and Mode Register (EMR)
      • 3.1.2.1 Clearing EMR Bits
  • 3.2 PLL and Clock Registers
• Chapter4 Emulation and Debug (EOnCE)
  • 4.1 Debugging System
  • 4.2 Overview of the Combined JTAG and EOnCE Interface
    • 4.2.1 Cascading Multiple SC140 EOnCE Modules in a SoC
    • 4.2.2 JTAG Scan Paths
    • 4.2.3 Activating the EOnCE Through the JTAG Port
    • 4.2.4 Enabling the EOnCE Module
    • 4.2.5 DEBUG_REQUEST and ENABLE_EONCE Commands
    • 4.2.6 Reading/Writing EOnCE Registers Through JTAG
  • 4.3 Main Capabilities of the EOnCE Module
    • 4.3.1 EOnCE Signals
    • 4.3.2 EOnCE Dedicated Instructions
    • 4.3.3 Debug State
    • 4.3.4 Debug Exception
    • 4.3.5 Executing an Instruction while in Debug State
    • 4.3.6 Software Downloading
    • 4.3.7 EOnCE Events
    • 4.3.8 EOnCE Actions
    • 4.3.9 Event and Action Summary
  • 4.4 EOnCE Enabling and Power Considerations
  • 4.5 EOnCE Module Internal Architecture
    • 4.5.1 EOnCE Controller
    • 4.5.2 Event Counter
    • 4.5.3 Event Detection Unit (EDU)
      • 4.5.3.1 Address Event Detection Channel (EDCA)
      • 4.5.3.2 Data Event Detection Channel (EDCD)
      • 4.5.3.3 Optional External Event Detection Address Channels
    • 4.5.4 Event Selector (ES)
    • 4.5.5 Trace Unit
      • 4.5.5.1 Change of Flow and Interrupt Tracing
      • 4.5.5.2 Writing to the Trace Buffer
      • 4.5.5.3 Reading the Trace Buffer (TB_BUFF)
      • 4.5.5.4 Trace Unit Programming Model
  • 4.6 EOnCE Register Addressing
    • 4.6.1 Reading or Writing EOnCE Registers Using Core Software
    • 4.6.2 Real-Time JTAG Access
    • 4.6.3 Real-Time Data Transfer
    • 4.6.4 General EOnCE Register Issues
  • 4.7 EOnCE Controller Registers
    • 4.7.1 EOnCE Command Register (ECR)
    • 4.7.2 EOnCE Status Register (ESR)
    • 4.7.3 EOnCE Monitor and Control Register (EMCR)
    • 4.7.4 EOnCE Receive Register (ERCV)
    • 4.7.5 EOnCE Transmit Register (ETRSMT)
    • 4.7.6 EE Signals
      • 4.7.6.1 EE Signals as Outputs
      • 4.7.6.2 EE Signals as Inputs
      • 4.7.6.3 EE Signals Control Register (EE_CTRL)
    • 4.7.7 Core Command Register (CORE_CMD)
    • 4.7.8 PC of the Exception ExecutionSet (PC_EXCP)
    • 4.7.9 PC of the Next ExecutionSet (PC_NEXT)
    • 4.7.10 PC of Last ExecutionSet (PC_LAST)
    • 4.7.11 PC Breakpoint Detection Register (PC_DETECT)
  • 4.8 Event Counter Registers
    • 4.8.1 Event Counter Control Register (ECNT_CTRL)
    • 4.8.2 Event Counter Value Register (ECNT_VAL)
    • 4.8.3 Extension Counter Value Register (ECNT_EXT)
    • 4.8.4 EC Signals
  • 4.9 Event Detection Unit (EDU) Channels and Registers
    • 4.9.1 Address Event Detection Channel (EDCA)
      • 4.9.1.1 EDCA Control Registers (EDCAi_CTRL)
      • 4.9.1.2 EDCA Reference Value Registers A and B (EDCAi_REFA, EDCAi_REFB)
      • 4.9.1.3 EDCA Mask Register (EDCAi_MASK)
    • 4.9.2 Data Event Detection Channel (EDCD)
      • 4.9.2.1 EDCD Control Register (EDCD_CTRL)
      • 4.9.2.2 EDCD Reference Value Register (EDCD_REF)
      • 4.9.2.3 EDCD Mask Register (EDCD_MASK)
  • 4.10 Event Selector (ES) Registers
    • 4.10.1 Event Selector Control Register (ESEL_CTRL)
    • 4.10.2 Event Selector Mask Debug State Register (ESEL_DM)
    • 4.10.3 Event Selector Mask Debug Exception Register (ESEL_DI)
    • 4.10.4 Event Selector Mask Enable Trace Register (ESEL_ETB)
    • 4.10.5 Event Selector Mask Disable Trace Register (ESEL_DTB)
  • 4.11 Trace Unit Registers
    • 4.11.1 Trace Buffer Control Register (TB_CTRL)
    • 4.11.2 Trace Buffer Read Pointer Register (TB_RD)
    • 4.11.3 Trace Buffer Write Pointer Register (TB_WR)
    • 4.11.4 Trace Buffer Register (TB_BUFF)
• Chapter5 Program Control
  • 5.1 Pipeline
    • 5.1.1 Instruction Pipeline Stages
      • 5.1.1.1 Instruction Pre-Fetch and Fetch
      • 5.1.1.2 Instruction Dispatch
      • 5.1.1.3 Address Generation
      • 5.1.1.4 Execution
  • 5.2 Instruction Grouping
    • 5.2.1 Grouping Types
      • 5.2.1.1 Serial Grouping
      • 5.2.1.2 Prefix Grouping
    • 5.2.2 Prefix Types
      • 5.2.2.1 Two-Word Prefix
      • 5.2.2.2 One-Word Low Register Prefix
    • 5.2.3 Conditional Execution
    • 5.2.4 Prefix Selection Algorithm
    • 5.2.5 Instruction Reordering Within an Execution Set
  • 5.3 Instruction Timing
    • 5.3.1 Sequential Instruction Timing
      • 5.3.1.1 DALU Instruction Timing
      • 5.3.1.2 Move Instruction Timing
      • 5.3.1.3 Bit Mask Instruction Timing
    • 5.3.2 Change-Of-Flow Instruction Timing
      • 5.3.2.1 Direct, PC-Relative, and Conditional COF
      • 5.3.2.2 Delayed COF
      • 5.3.2.3 COF Execution Cycles
    • 5.3.3 Memory Access Timing
      • 5.3.3.1 Memory Access Examples
      • 5.3.3.2 Implicit Push/Pop Memory Timing
      • 5.3.3.3 Memory Stall Conditions
  • 5.4 Hardware Loops
    • 5.4.1 Loop Programming Model
      • 5.4.1.1 Loop Start Address Registers (SAn)
      • 5.4.1.2 Loop Counter Registers (LCn)
      • 5.4.1.3 Status Register (SR) Loop Flag Bits
    • 5.4.2 Loop Notation and Encoding
    • 5.4.3 Loop Initiation and Execution
    • 5.4.4 Loop Nesting
    • 5.4.5 Loop Iteration and Termination
    • 5.4.6 Loop Control Instructions
    • 5.4.7 Loop Timing
  • 5.5 Stack Support
    • 5.5.1 SC140 Single Stack Memory Use
    • 5.5.2 SC140 Dual Stack Memory Use
    • 5.5.3 Stack Support Instructions
    • 5.5.4 Shadow Stack Pointer Registers
    • 5.5.5 Fast Return from Subroutines
  • 5.6 Working Modes
    • 5.6.1 Normal Working Mode
    • 5.6.2 Exception Working Mode
    • 5.6.3 Typical Working Mode Usage Scenarios
      • 5.6.3.1 Dual-stack RTOS
      • 5.6.3.2 Single-stack RTOS
    • 5.6.4 Working Mode Transitions
      • 5.6.4.1 From Exception to Normal mode
      • 5.6.4.2 From Normal to Exception mode
  • 5.7 Processing States
    • 5.7.1 Processing State Change Instructions
    • 5.7.2 Processing State Transitions
    • 5.7.3 Execution State
    • 5.7.4 Reset Processing State
    • 5.7.5 Debug State
    • 5.7.6 Wait Processing State
    • 5.7.7 Stop Processing State
  • 5.8 Exception Processing
    • 5.8.1 Interrupt Vector Address
      • 5.8.1.1 Vector Base Address Register
      • 5.8.1.2 Programming Exception Routine Addresses
    • 5.8.2 Return From Exception Instructions
    • 5.8.3 Maskable Interrupts
      • 5.8.3.1 Interrupt Priority Level
      • 5.8.3.2 Controlling All Interrupt Sources
    • 5.8.4 Non-Maskable Interrupts (NMI)
    • 5.8.5 Internal Exceptions
      • 5.8.5.1 Illegal Exception
      • 5.8.5.2 DALU Overflow
      • 5.8.5.3 TRAP Exception
      • 5.8.5.4 Debug Exception
    • 5.8.6 Exception Interface to the Pipeline
      • 5.8.6.1 Exception Routine Fetch
      • 5.8.6.2 Exception Mode Execution
    • 5.8.7 Exception Timing
• Chapter6 Instruction Set Accelerator Plug-In
  • 6.1 Introduction
  • 6.2 ISAP - SC140 Schematic Connection
    • 6.2.1 Single ISAP
    • 6.2.2 Multiple ISAP
  • 6.3 ISAP instructions and instruction encoding
  • 6.4 ISAP Memory Access
  • 6.5 ISAP-core register transfers
  • 6.6 Immediate Data Transfer to ISAP registers
  • 6.7 Core Assembly Syntax with an ISAP
    • 6.7.1 Identification of ISAP instructions
      • 6.7.1.1 Working with One ISAP
      • 6.7.1.2 Working with Multiple ISAPs
    • 6.7.2 An Example of the Definition Flexibility of an ISAP
    • 6.7.3 Conditional Execution
  • 6.8 Programming Rules
    • 6.8.1 ISAP Functions that Interact With the Core
    • 6.8.2 Grouping rules for explicit ISAP instructions
    • 6.8.3 Rules for implicit AGU instructions
    • 6.8.4 Sequencing rules for T bit update
• Chapter7 Programming Rules
  • 7.1 VLES Sequencing Semantics
  • 7.2 VLES Grouping Semantics
  • 7.3 SC140 Pipeline Exposure
  • 7.4 Programming Rule Notation
    • 7.4.1 Grouping Rules
      • 7.4.1.1 Prefix Instructions
      • 7.4.1.2 Conditional Subgroups
      • 7.4.1.3 Assembler Reordering
    • 7.4.2 Sequencing Rules
      • 7.4.2.1 Cycle Counts
      • 7.4.2.2 Conditional Execution
      • 7.4.2.3 Simulator Execution Counts
    • 7.4.3 Register Read/Write
      • 7.4.3.1 Register Names
      • 7.4.3.2 B Register Aliasing
    • 7.4.4 Status Bit Updates
    • 7.4.5 Instruction Words
    • 7.4.6 MOVE-like Instructions
      • 7.4.6.1 Address/Data Operands
    • 7.4.7 AGU Arithmetic Instructions
    • 7.4.8 Change-Of-Flow Destinations
      • 7.4.8.1 COF Instructions
    • 7.4.9 Delayed COF Instructions
      • 7.4.9.1 Delay Slot
    • 7.4.10 Hardware Loops
      • 7.4.10.1 Enabled Loop
      • 7.4.10.2 Enveloping Loop
  • 7.5 Static Programming Rules
    • 7.5.1 Hardware Loop Detection
    • 7.5.2 General Grouping Rules
    • 7.5.3 Prefix Grouping Rules
    • 7.5.4 AGU Rules
    • 7.5.5 Delayed COF Rules
    • 7.5.6 Status Bit Rules
    • 7.5.7 Loop Nesting Rules
    • 7.5.8 Loop LA Rules
    • 7.5.9 Loop Sequencing Rules
    • 7.5.10 Loop COF Rules
    • 7.5.11 General Looping Rules
  • 7.6 Dynamic Programming Rules
    • 7.6.1 AGU Dynamic Rules
    • 7.6.2 Memory Access Rules
    • 7.6.3 RAS Rules
    • 7.6.4 Loop Rules
    • 7.6.5 Rule Detection Across COF Boundaries
      • 7.6.5.1 Cycle-Based COF Rules
      • 7.6.5.2 VLES-Based COF Rules
    • 7.6.6 Rule Detection Across Exception Boundaries
  • 7.7 Programming Guidelines
    • 7.7.1 Rules Not Detected Across COF Boundaries
    • 7.7.2 Good Programming Practices
      • 7.7.2.1 Source Code Practices
      • 7.7.2.2 Binary Code Practices
      • 7.7.2.3 Software Development Practices
  • 7.8 LPMARK Rules
    • 7.8.1 LPMARK Instruction Type
    • 7.8.2 Static Programming Rules
      • 7.8.2.1 General Grouping Rules
      • 7.8.2.2 Prefix Grouping Rules
    • 7.8.3 Dynamic Programming Rules
      • 7.8.3.1 LPMARK Notation
      • 7.8.3.2 Loop Nesting Rules
      • 7.8.3.3 Loop LA Rules
      • 7.8.3.4 Loop Sequencing Rules
      • 7.8.3.5 Loop COF Rules
      • 7.8.3.6 General Looping Rules
      • 7.8.3.7 Rule Detection Across Exception Boundaries
    • 7.8.4 LPMARK Programming Guidelines
  • 7.9 NOP Definition
    • 7.9.1 Grouping Examples
• AppendixA SC140 DSP Core Instruction Set
  • A.1 Introduction
    • A.1.1 Conventions
      • A.1.1.1 Brackets as ISAP indicators
      • A.1.1.2 Brackets as address indicators
    • A.1.2 Addressing Mode Notation
    • A.1.3 Data Representation in Memory for the Examples
    • A.1.4 Encoding Notation
    • A.1.5 Prefix Word Encoding
      • A.1.5.1 One-Word Low Register Prefix
      • A.1.5.2 Two-Word Prefix
    • A.1.6 Instruction Types
      • A.1.6.1 Instruction Sub-types
  • A.2 Instructions
    • A.2.1 Instruction Definition Layout
      • ABS
      • ADC
      • ADD
      • ADD2
      • ADDA
      • ADDL1A
      • ADDL2A
      • ADDNC.W
      • ADR
      • AND
      • AND
      • AND.W
      • ASL
      • ASL2A
      • ASLA
      • ASLL
      • ASLW
      • ASR
      • ASRA
      • ASRR
      • ASRW
      • BF
      • BFD
      • BMCHG
      • BMCHG.W
      • BMCLR
      • BMCLR.W
      • BMSET
      • BMSET.W
      • BMTSET
      • BMTSET.W
      • BMTSTC
      • BMTSTC.W
      • BMTSTS
      • BMTSTS.W
      • BRA
      • BRAD
      • BREAK
      • BSR
      • BSRD
      • BT
      • BTD
      • CLB
      • CLR
      • CMPEQ
      • CMPEQ.W
      • CMPEQA
      • CMPGT
      • CMPGT.W
      • CMPGTA
      • CMPHI
      • CMPHIA
      • CONT
      • CONTD
      • DEBUG
      • DEBUGEV
      • DECA
      • DECEQ
      • DECEQA
      • DECGE
      • DECGEA
      • DI
      • DIV
      • DMACSS
      • DMACSU
      • DOENn
      • DOENSHn
      • DOSETUPn
      • EI
      • EOR
      • EOR
      • EOR.W
      • EXTRACT
      • EXTRACTU
      • IADDNC.W
      • IFc
      • ILLEGAL
      • IMAC
      • IMACLHUU
      • IMACUS
      • IMPY
      • IMPY.W
      • IMPYHLUU
      • IMPYSU
      • IMPYUU
      • INC
      • INC.F
      • INCA
      • INSERT
      • JF
      • JFD
      • JMP
      • JMPD
      • JSR
      • JSRD
      • JT
      • JTD
      • LPMARKx
      • LSLL
      • LSR
      • LSRA
      • LSRR
      • LSRW
      • MAC
      • MACR
      • MACSU
      • MACUS
      • MACUU
      • MARK
      • MAX
      • MAX2
      • MAX2VIT
      • MAXM
      • MIN
      • MOVE.2F
      • MOVE.2L
      • MOVE.2W
      • MOVE.4F
      • MOVE.4W
      • MOVE.B
      • MOVE.F
      • MOVE.L
      • MOVE.L
      • MOVE.L
      • MOVE.W
      • MOVE.W
      • MOVEc
      • MOVES.2F
      • MOVES.4F
      • MOVES.F
      • MOVEU.B
      • MOVEU.L
      • MOVEU.W
      • MOVEU.W
      • MPY
      • MPYR
      • MPYSU
      • MPYUS
      • MPYUU
      • NEG
      • NOP
      • NOT
      • NOT
      • NOT.W
      • OR
      • OR
      • OR.W
      • POP
      • POPN
      • PUSH
      • PUSHN
      • RND
      • ROL
      • ROR
      • RTE
      • RTED
      • RTS
      • RTSD
      • RTSTK
      • RTSTKD
      • SAT.F
      • SAT.L
      • SBC
      • SBR
      • SKIPLS
      • STOP
      • SUB
      • SUB2
      • SUBA
      • SUBL
      • SUBNC.W
      • SXT.x
      • SXTA.x
      • TFR
      • TFRA
      • TFRA
      • TFRc
      • TSTEQ
      • TSTEQA.x
      • TSTGE
      • TSTGEA.L
      • TSTGT
      • TSTGTA
      • VSL
      • WAIT
      • ZXT.x
      • ZXTA.x
• AppendixB StarCore Registry
  • B.1 Using the StarCore Registry
• Index