BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 105)

PDI Description
Slave Controller – IP Core for Xilinx FPGAs III-93
10.1.2 Configuration
The Digital I/O interface is selected with PDI type 0x04 in the PDI control register 0x0140. It supports
different configurations, which are located in registers 0x0150
– 0x0153.
10.1.3 Digital Inputs
Digital input values appear in the process memory at address 0x1000:0x1003. EtherCAT devices use
Little Endian byte ordering, so I/O[7:0] can be read at 0x1000 etc. Digital inputs are written to the
process memory by the Digital I/O PDI using standard PDI write operations.
Digital inputs can be configured to be sampled by the ESC in four ways:

Digital inputs are sampled at the start of each Ethernet frame, so that EtherCAT read commands
to address 0x1000:0x1003 will present digital input values sampled at the start of the same frame.
The SOF signal can be used externally to update the input data, because the SOF is signaled
before input data is sampled.

The sample time can be controlled externally by using the LATCH_IN signal. The input data is
sampled by the ESC each time a rising edge of LATCH_IN is recognized.

Digital inputs are sampled at Distributed Clocks SYNC0 events.

Digital inputs are sampled at Distributed Clocks SYNC1 events.
For Distributed Clock SYNC input, SYNC generation must be activated (register 0x0981). SYNC
output is not necessary (register 0x0151). SYNC pulse length (registers 0x0982:0x0983) should not be
set to 0, because acknowledging of SYNC events is not possible with Digital I/O PDI. Sample time is
the beginning of the SYNC event.
10.1.4 Digital Outputs
Digital Output values have to be written to register 0x0F00:0x0F03 (register 0x0F00 controls I/O[7:0]
etc.). Digital Output values are not read by the Digital I/O PDI using standard read commands,
instead, there is a direct connection for faster response times.
The process data watchdog (register 0x0440) has to be either active or disabled; otherwise digital
outputs will not be updated. Digital outputs can be configured to be updated in four ways:

Digital Outputs are updated at the end of each EtherCAT frame (EOF mode).

Digital outputs are updated with Distributed Clocks SYNC0 events (DC SYNC0 mode).

Digital outputs are updated with Distributed Clocks SYNC1 events (DC SYNC1 mode).

Digital Outputs are updated at the end of an EtherCAT frame which triggered the Process Data
Watchdog (with typical SyncManager configuration: a frame containing a write access to at least
one of the registers 0x0F00:0x0F03). Digital Outputs are only updated if the EtherCAT frame was
correct (WD_TRIG mode).
For Distributed Clock SYNC output, SYNC generation must be activated (register 0x0981). SYNC
output is not necessary (register 0x0151). SYNC pulse length (registers 0x0982:0x0983) should not be
set to 0, because acknowledging of SYNC events is not possible with Digital I/O PDI. Output time is
the beginning of the SYNC event.
An output event is always signaled by a pulse on OUTVALID even if the digital outputs remain
unchanged.
For output data to be visible on the I/O signals, the following conditions have to be met:

SyncManager watchdog must be either active (triggered) or disabled.

OE_EXT (Output enable) must be high.

Output values have to be written to the registers 0x0F00:0x0F03 within a valid EtherCAT frame.

The configured output update event must have occurred.