BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 87)

IP Core Signals
Slave Controller – IP Core for Xilinx FPGAs III-75
Table 33: PLB PDI additional signals of XPS/EDK pcores
Condition Name Direction Description
PLB PRODUCT_ID0 GENERIC Product ID value
PRODUCT_ID1 GENERIC Product ID value
PRODUCT_ID2 GENERIC Product ID value
PRODUCT_ID3 GENERIC Product ID value
NUM_FMMU GENERIC Number of FMMUs (0-8)
NUM_SYNC GENERIC Numer of SyncManagers
(0-8)
SIZE_DPRAM GENERIC Size of Process Data RAM
(0/1/2/4/8/16/32/60)
PROM_CLK_O OUTPUT Equals
PROM_CLK
PROM_CLK_T OUTPUT 0: enable output driver for
PROM_CLK_O
1: disable output driver for
PROM_CLK_O
PROM_DATA_I INPUT Equals
PROM_DATA_IN
PROM_DATA_O OUTPUT Equals
PROM_DATA_OUT
PROM_DATA_T OUTPUT Equals
NOT(PROM_DATA_ENA)
MDIO_I INPUT Equals
MDIO_DATA_IN
MDIO_O OUTPUT Equals
MDIO_DATA_OUT
MDIO_T OUTPUT Equals
NOT(MDIO_DATA_ENA)
NOTE: The PROM_CLK/PROM_DATA/MDIO signals with suffix _I/_O/_T are duplicates of the general tristate
signals _IN/_OUT/_ENA of PROM_CLK/PROM_DATA/MDIO_DATA. They are introduced because XPS expects
the suffixes _I/_O/_T for tristate drivers. Use either all _IN/_OUT_ENA signals or all _I/_O/_T signals. Connect
unused inputs to ‘0’ (they have in internal logic OR).