BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 128)

PDI Description
III-116 Slave Controller – IP Core for Xilinx FPGAs
BHE1
CS
BHE
WR
RD
DATA
BUSY
ADR1 ADR
t WR_active
t CS_delay
t WR_delay
t
ADR_BHE_DATA_hold
DATA1
t
ADR_BHE_DATA_setup
t
CS_to_BUSY
t
WR_to_BUSY
t
CS_to_BUSY
t
CS_to_BUSY
t
BUSY_to_WR_CS
Internal
state
Writing ADR1 Idle Idle
t
CS_WR_overlap
t
write_int
Writing ADR2
BHE2
ADR2
DATA2
t
BUSY_to_WR_CS
t
CS_WR_overlap
Idle
t
write_int
Figure 56: Write access (write after falling edge nWR)