BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 74)

IP Core Signals
III-62 Slave Controller – IP Core for Xilinx FPGAs
8.4 Distributed Clocks SYNC/LATCH Signals
Table 21 lists the signals used with Distributed Clocks.
Table 21: DC SYNC/LATCH signals
Condition Name Direction Description
Distributed Clocks and
SYNC0 enabled
SYNC_OUT0 OUTPUT DC sync output 0
Distributed Clocks and
SYNC0+1 enabled
SYNC_OUT1 OUTPUT DC sync output 1
Distributed Clocks and
Latch0 enabled
LATCH_IN0 INPUT DC latch input 0
Distributed Clocks and
Latch0+1 enabled
LATCH_IN1 INPUT DC latch input 1
NOTE: SYNC_OUT0/1 are active high/push-pull outputs.