BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 106)

PDI Description
III-94 Slave Controller – IP Core for Xilinx FPGAs
32
Output register
Digital I/O output
data register
0x0F00:0x0F03
Watchdog
&
32
32 EOF
DC Sync0
DC Sync1
Digital output pins
OE_EXT
D Q
Output event
configuration
Output event occured
since watchdog active
Figure 38: Digital Output Principle Schematic
NOTE: The Digital Outputs are not driven (high impedance) until the EEPROM is loaded. Depending on the
FPGA configuration, Digital Outputs (like all other FPGA user pins) might have pull-up resistors until the FPGA
has loaded its configuration. This behaviour has to be taken into account when using digital output signals.
10.1.5 Output Enable
The IP Core has an Output Enable signal OE_EXT. With the OE_EXT signal, the I/O signals can be
cleared. The I/O signals will be driven low after the output enable signal OE_EXT is set to low or the
SyncManager Watchdog is expired (and not disabled).
10.1.6 SyncManager Watchdog
The SyncManager watchdog (registers 0x0440:0x0441) must be either active (triggered) or disabled
for output values to appear on the I/O signals. The SyncManager Watchdog is triggered by an
EtherCAT write access to the output data registers.
If the output data bytes are written independently, a SyncManager with a length of 1 byte is used for
each byte of 0x0F00:0x0F03 containing output bits (SyncManager N configuration: buffered mode,
EtherCAT write/PDI read, and Watchdog Trigger enabled: 0x44 in register 0x0804+N*8). Alternatively,
if all output data bits are written together in one EtherCAT command, one SyncManager with a length
of 1 byte is sufficient (SyncManager N configuration: buffered mode, EtherCAT write/PDI read, and
Watchdog Trigger enabled: 0x44 in register 0x0804+N*8). The start address of the SyncManager
should be one of the 0x0F00:0x0F03 bytes containing output bits, e.g., the last byte containing output
bits.
The SyncManager Watchdog can also be disabled by writing 0 into registers 0x0420:0x0421.
The Watchdog Mode configuration bit is used to configure if the expiration of the SyncManager
Watchdog will have an immediate effect on the I/O signals (output reset immediately after watchdog
timeout) or if the effect is delayed until the next output event (output reset with next output event). The
latter case is especially relevant for Distributed Clock SYNC output events, because any output
change will occur at the configured SYNC event.
Immediate output reset after watchdog timeout is not available if OUTVALID mode set to watchdog
trigger (0x0150[1]=1).
For external watchdog implementations, the WD_TRIG (watchdog trigger) signal can be used. A
WD_TRIG pulse is generated if the SyncManager Watchdog is triggered. In this case, the internal
SyncManager Watchdog should be disabled, and the external watchdog may use OE_EXT to reset
the I/O signals if the watchdog is expired. For devices without the WD_TRIG signal, OUTVALID can
be configured to reflect WD_TRIG.