BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 19)

Overview
Slave Controller – IP Core for Xilinx FPGAs III-7
Version Release notes
3.00f
(2/2014)
Restrictions of previous versions which are removed in this version:

The AXI PDI writes correct data if simultaneous read and write accesses occur
repeatedly.

RX FIFO size is properly initialized by SII EEPROM
Restrictions of this version, which are removed in V3.00g:

The ERR LED does not allow overriding using the ERR LED Override register
0x0139 while AL Status register Error Indication bit 0x0130[4] is set

RMII is not supported because of wrong configuration by IPCore_Config tool
Restrictions of this version, which are removed in V3.00j:

The AXI PDI may not complete an access occasionally if overlapping read and write
accesses occur, causing the processor to wait endlessly.

The AXI PDI does not execute read accesses correctly if ARSIZE is smaller than
the AXI bus width.
Restrictions of this version, which are removed in V3.00k:

The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) cannot be used in the 60
Kbyte RAM configuration.

The AXI PDI may write to wrong bytes if the write data is valid before the address,
which is typically true for AXI4LITE.

The AXI PDI may read additional bytes after the intended bytes.

The PLB PDI only supports peer-to-peer mode (C_SPLB_P2P=1), or a base
address of 0 (C_SPLB_BASEADDR=0x00000000).

The PLB PDI was generated with an invalid component declaration package.
3.00g
(4/2014) Enhancements:

The Sync/Latch PDI Configuration register 0x0151 shows the same value as
previous IP Core versions. The actual configuration is not affected, since it is fixed
by the IP Core configuration.

Added support for unaligned AXI burst transfers.

Internal license attribute encoding updated (issues with Vivado 2012.x)
Restrictions of previous versions which are removed in this version:

The ERR LED allows overriding using the ERR LED Override register 0x0139 while
AL Status register Error Indication bit 0x0130[4] is set. The override flag is now
cleared upon a rising edge of 0x0130[4], and it can be set again afterwards.

RMII is now configured correctly by IPCore_Config tool
Restrictions of this version, which are removed in V3.00j:

The AXI PDI may not complete an access occasionally if overlapping read and write
accesses occur, causing the processor to wait endlessly.

The AXI PDI does not execute read accesses correctly if ARSIZE is smaller than
the AXI bus width.
Restrictions of this version, which are removed in V3.00k:

The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) cannot be used in the 60
Kbyte RAM configuration.

The AXI PDI may write to wrong bytes if the write data is valid before the address,
which is typically true for AXI4LITE.

The AXI PDI may read additional bytes after the intended bytes.

The PLB PDI only supports peer-to-peer mode (C_SPLB_P2P=1), or a base
address of 0 (C_SPLB_BASEADDR=0x00000000).

The PLB PDI was generated with an invalid component declaration package.