BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 51)

IP Core Configuration
Slave Controller – IP Core for Xilinx FPGAs III-39
Mapping to global IRQ
Sync0 and Sync1 can additionally be mapped internally to the global IRQ. This might be a good
solution if a microcontroller interface is short on IRQs. However, the sync signals will remain available
on Sync0 and Sync1 outputs.