BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 69)

FPGA Resource Consumption
Slave Controller – IP Core for Xilinx FPGAs III-57
Table 16: Approximate resource requirements for main configurable functions
Configurable Function Reg. LUT6 Details
Minimum Configuration 2,300 2,200 0 x SM, 0 x FMMU, no features, no DC, PDI:
32 Bit digital I/O, 1 kByte DPRAM, 1 port MII
Maximum Configuration 16,200 21,300 8 x SM, 8 x FMMU, all features except for
EEPROM Emulation and System Time PDI
controlled, DC 64 bit, PDI: SPI, GPIO, 60
kByte DPRAM, 3 ports MII
Additional port 700 650 all port features enabled (without DC Receive
time)
PHY features 500 550 All MII features: Management Interface, MI link
detection and configuration, TX Shift, and
enhanced link detection (3 ports)
SyncManager 400 800 per SyncManager
FMMU 400 450 per FMMU
DPRAM 50 200 60 KB
Distributed Clocks 100 50 Receive time per port
900 800 System time (32 bit)
1,000 1,400 SyncSignals (32 bit)
600 750 LatchSignals (32 bit)
1,200 1,100 System time (64 bit)
1,600 2,500 SyncSignals (64 bit)
1,200 1,200 LatchSignals (64 bit)
350 350 SyncManager Event Times
Feature details 550 800 all features except for EEPROM Emulation and
SyncManager Event Times
PDI
32 Bit Digital I/O 300 400
SPI 650 1,800
8 Bit µController 350 1,350
16 Bit µController 500 1,750
PLB 400 1,600 25 MHz, 32 Bit
AXI4 LITE 450 1,800 25 MHz, 32 Bit
AXI4 550 2,250 25 MHz, 32 Bit
GPIO 300 150 8 Byte