BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 132)

PDI Description
III-120 Slave Controller – IP Core for Xilinx FPGAs
PLB_SPLB_CLK
PLB_ABus ADR
PLB_RNW
PLB_Sl_RdDack
PLB_Sl_RdComp
PLB_Sl_rdDBus DATA
t
Read
PLB_PAValid
t
Clk
PLB_Sl_addrAck
PLB_BE BE
PLB_Sl_Mbusy[x]
Figure 58: PLB Read Access
PLB_SPLB_CLK
PLB_ABus ADR
PLB_RNW
PLB_Sl_wrDack
PLB_Sl_wrComp
t
Write
PLB_PAValid
t Clk
PLB_Sl_addrAck
PLB_BE BE
PLB_Sl_Mbusy[x]
PLB_wrDBus DATA
Figure 59: PLB Write Access