BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 53)

IP Core Configuration
Slave Controller – IP Core for Xilinx FPGAs III-41
PDI SM/IRQ acknowledge by WRITE
Some ESC functions are triggered by reading from the PDI. Since PDI data bus widths are increasing
up to 64 bit and beyond, it is not possible to read individual bytes anymore because most µControllers
do not support byte enable signals for read commands. In order to prevent accidentally reading of
trigger addresses (like SyncManager buffer end or IRQ acknowledge registers), this option allows to
use write commands (with byte enables) to trigger the functions.
SyncManager Event Times
Distributed Clocks SyncManager Event Times (0x09F0:0x09FF) are available if checked. Used for
debugging SyncManager interactions.
EPU and PDI Error Counter
EtherCAT Processing Unit (EPU) and PDI Error counters (0x030C:0x030D) are available if checked.
Lost Link Counter
Lost Link Counters (0x0310:0x0313) are available if checked.
EEPROM Emulation by PDI
EEPROM is and has to be emulated by a µController with access to a NVRAM. I²C EEPROM is not
necessary if EEPROM Emulation is activated, I²C interface is deactivated. Only usable with PDIs for
µController connection.
RESET slave by ECAT/PDI
The reset registers (0x0040:0x0041) and the RESET_OUT signal is available if this feature is
checked.
RUN LED (Device State)
RUN LED output indicates AL Status (0x0130) if activated. Otherwise RUN LED has to be controlled
by a µController. Always activated if no PDI is selected or if Digital I/O PDI is selected.
Extended RUN/ERR LED
Support for ERR LED and STATE LED, direct control of RUN/ERR LED via RUN/ERR LED Override
register (0x0138:0x0139).
LED Test
A short LED flash after reset for all LED signals is enabled if this feature is selected.