BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 134)

PDI Description
III-122 Slave Controller – IP Core for Xilinx FPGAs
Signal
Directio
n
Description Channel
Signal
polarity
PDI_AXI_ARPROT[2:0] INPUT Read protection type RD addr.
PDI_AXI_ARREGION[3:0] INPUT Read region identifier RD addr.
PDI_AXI_ARQOS[3:0] INPUT Read QoS identifier RD addr.
PDI_AXI_ARVALID INPUT Read address valid RD addr. act. high
PDI_AXI_ARREADY OUTPUT Read address ready RD addr. act. high
PDI_AXI_RDATA
[PDI_EXT_BUS_WIDTH-1:0] OUTPUT Read data RD data
PDI_AXI_RRESP[1:0] OUTPUT Read response RD data
PDI_AXI_RVALID OUTPUT Read data valid RD data act. high
PDI_AXI_RREADY INPUT Read data ready RD data act. high
PDI_AXI_IRQ_MAIN OUTPUT Interrupt
Table 62: Additional AXI4 signals
Signal
Directio
n
Description Channel
Signal
polarity
PDI_AXI_AWID
[PDI_BUS_ID_WIDTH-1:0] INPUT Write address ID WR addr.
PDI_AXI_AWLEN[7:0] INPUT Write length WR addr.
PDI_AXI_AWSIZE[2:0] INPUT Write size WR addr.
PDI_AXI_AWBURST[1:0] INPUT Write burst type WR addr.
PDI_AXI_AWLOCK INPUT Write lock WR addr.
PDI_AXI_AWCACHE[3:0] INPUT Write cache type WR addr.
PDI_AXI_WLAST INPUT Write data last WR data act. high
PDI_AXI_BID
[PDI_BUS_ID_WIDTH-1:0] OUTPUT Write response ID WR resp.
PDI_AXI_ARID
[PDI_BUS_ID_WIDTH-1:0] INPUT Read address ID RD addr.
PDI_AXI_ARLEN[7:0] INPUT Read length RD addr.
PDI_AXI_ARSIZE[2:0] INPUT Read size RD addr.
PDI_AXI_ARBURST[1:0] INPUT Read burst type RD addr.
PDI_AXI_ARLOCK INPUT Read lock RD addr.
PDI_AXI_ARCACHE[3:0] INPUT Read cache type RD addr.
PDI_AXI_RID
[PDI_BUS_ID_WIDTH-1:0] OUTPUT Read data ID RD data
PDI_AXI_RLAST OUTPUT Read data last RD data act. high
Please refer to the AMBA AXI and ACE Protocol Specification from ARM ® for details about the
AXI4/AXI4 LITE bus ( http://www.arm.com ).