BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 20)

Overview
III-8 Slave Controller – IP Core for Xilinx FPGAs
Version Release notes
3.00j
(9/2014) Enhancements:

An example design for the Xilinx Zynq ZC702 development kit using Vivado has
been added. A Vivado SDK template for this example design is included

The example designs using ISMNET PHY boards have been extended to support
COL and CRS signals, which are required for proper PHY configuration.
 The PDI watchdog status 0x0110[1] now shows value ‘1’ (watchdog reloaded) if the
PDI watchdog is configured to be not available.

The ESI XML device description does not use special data types anymore.
Restrictions of previous versions which are removed in this version:

The AXI PDI completes accesses if overlapping read and write accesses occur.

The AXI PDI executes read accesses correctly if ARSIZE is smaller than the AXI
bus width.
Restrictions of this version, which are removed in V3.00k:

The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) cannot be used in the 60
Kbyte RAM configuration.

The AXI PDI may write to wrong bytes if the write data is valid before the address,
which is typically true for AXI4LITE.

The AXI PDI may read additional bytes after the intended bytes.

The PLB PDI only supports peer-to-peer mode (C_SPLB_P2P=1), or a base
address of 0 (C_SPLB_BASEADDR=0x00000000).

The PLB PDI was generated with an invalid component declaration package.
3.00k
(1/2015)
The PlanAhead-based Xilinx Zynq ZC702 example design has been removed, because
a Vivado based example design is available.
Enhancements:

For EEPROM Emulation, the CRC error bit 0x0502[11] can be written via PDI to
indicate CRC errors during a reload command.

The IPCore_Config tool optionally generates AXI/PLB configurations without the
XPS pcores folder structure (e.g. for Vivado).

The AXI4LITE PDI wrapper does no longer contain the unused REGION and QOS
signals.
Restrictions of previous versions which are removed in this version:

The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) can be used in the 60 Kbyte
RAM configuration.

The AXI PDI does not write to wrong bytes if the write data is valid before the
address.

The AXI PDI does not read additional bytes after the intended bytes.

The PLB PDI supports any base address.

The PLB PDI is generated with a valid component declaration package.