BECKHOFF EtherCAT IP Core for Xilinx FPGAs v3.00k - Manual (Page 61)

Example Designs
Slave Controller – IP Core for Xilinx FPGAs III-49
6 Example Designs
Example designs are available for:

Avnet Xilinx Spartan-6 LX150T Development Kit with MII and Digital I/O PDI

Avnet Xilinx Spartan-6 LX150T Development Kit with MII, AXI PDI, and Microblaze processor

Xilinx Zynq ZC702 Development Kit with MII, AXI PDI, and ARM processor (Vivado based)
The EtherCAT master uses an XML file which describes the device and its features. The XML device
description file for all example designs and its schema can be found in the installation directory.
<IPInst_dir>\example_designs\EtherCAT_Device_Description\
Projects have to be compiled and then can be loaded to the SPI configuration EEPROM of the
evaluation board.
The EtherCAT IP core resource consumption figures are based on EtherCAT IP Core for Xilinx FPGAs
Version 3.00c and Xilinx ISE 14.5.
PHY strapping options on Xilinx ISMNET PHY board
Some Ethernet PHYs, and especially the PHYs on the Xilinx ISMNET PHY board use the
communication signals for strapping configuration signals. If these signals are not used by the FPGA
design, take care that the strapping values are not changed by default IO behaviour.
Due to this fact, the COL and CRS signals of the PHYs are declared as inputs in the example designs.
In this way, these two signals are not driven or pulled up/down by the FPGA, so the configuration
resistors on the ISMNET define the configuration.